mirror of https://github.com/YosysHQ/yosys.git
Improved handling of init values in opt_rmdff
based on a patch by Mingyu Gao, user gaomy3832 on github
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parent
8cdbcf6859
commit
9041f34233
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@ -83,26 +83,24 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
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}
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if (dff->type == "$dff" && mux_drivers.has(sig_d) && !has_init) {
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if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
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std::set<RTLIL::Cell*> muxes;
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mux_drivers.find(sig_d, muxes);
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for (auto mux : muxes) {
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RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B"));
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if (sig_a == sig_q && sig_b.is_fully_const()) {
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RTLIL::SigSig conn(sig_q, sig_b);
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mod->connect(conn);
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if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) {
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mod->connect(sig_q, sig_b);
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goto delete_dff;
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}
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if (sig_b == sig_q && sig_a.is_fully_const()) {
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RTLIL::SigSig conn(sig_q, sig_a);
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mod->connect(conn);
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if (sig_b == sig_q && sig_a.is_fully_const() && (!has_init || val_init == sig_a.as_const())) {
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mod->connect(sig_q, sig_a);
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goto delete_dff;
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}
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}
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}
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if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) {
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if (sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (val_rv.bits.size() == 0)
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val_rv = val_init;
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RTLIL::SigSig conn(sig_q, val_rv);
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@ -110,7 +108,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && sig_r.size() && !has_init) {
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if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connect(conn);
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goto delete_dff;
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@ -122,13 +120,13 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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goto delete_dff;
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}
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if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
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if (sig_d.is_fully_const() && !sig_r.size() && (!has_init || val_init == sig_d.as_const())) {
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RTLIL::SigSig conn(sig_q, sig_d);
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mod->connect(conn);
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goto delete_dff;
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}
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if (sig_d == sig_q && !(sig_r.size() && has_init)) {
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if (sig_d == sig_q && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (sig_r.size()) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connect(conn);
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