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Fixed bug in synthesis of memories that are never written

This commit is contained in:
Clifford Wolf 2013-10-17 21:00:37 +02:00
parent c20571ca5e
commit 95dbacefbf
1 changed files with 7 additions and 2 deletions
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9
passes/memory/memory_map.cc
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@ -121,8 +121,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->name = genid(cell->name, "", i);
c->type = "$dff";
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
c->connections["\\CLK"] = clocks.extract(0, 1);
if (clocks_pol.bits.size() > 0) {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
c->connections["\\CLK"] = clocks.extract(0, 1);
} else {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
}
module->cells[c->name] = c;
RTLIL::Wire *w_in = new RTLIL::Wire;