mirror of https://github.com/YosysHQ/yosys.git
Added iopadmap pass
This commit is contained in:
Clifford Wolf
parent
b6db2d9b33
commit
96e7abad48
7
README
7
README
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@ -232,7 +232,8 @@ Verilog Attributes and non-standard features
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- The "nolatches" attribute on modules or always-blocks
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prohibits the generation of logic-loops for latches. Instead
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all not explicitly assigned values default to x-bits.
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all not explicitly assigned values default to x-bits. This does
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not affect clocked storage elements such as flip-flops.
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- The "nosync" attribute on registers prohibits the generation of a
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storage element. The register itself will always have all bits set
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@ -246,6 +247,10 @@ Verilog Attributes and non-standard features
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passes to identify input and output ports of cells. The verilog backend
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also does not output placeholder modules on default.
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- The "keep" attribute on cells is used to mark cells that should never be
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removed by the optimizer. This is used for example for cells that have
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hidden connections that are not part of the netlist, such as IO pads.
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- In addition to the (* ... *) attribute syntax, yosys supports
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the non-standard {* ... *} attribute syntax to set default attributes
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for everything that comes after the {* ... *} statement. (Reset
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@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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wire2driver.insert(sig, cell);
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}
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}
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if (cell->type == "$memwr")
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if (cell->type == "$memwr" || cell->attributes.count("\\keep"))
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queue.insert(cell);
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unused.insert(cell);
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}
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@ -1,6 +1,7 @@
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OBJS += passes/techmap/techmap.o
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OBJS += passes/techmap/dfflibmap.o
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OBJS += passes/techmap/iopadmap.o
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OBJS += passes/techmap/libparse.o
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GENFILES += passes/techmap/stdcells.inc
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@ -0,0 +1,159 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct IopadmapPass : public Pass {
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IopadmapPass() : Pass("iopadmap", "technology mapping of flip-flops") { }
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virtual void help()
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{
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log("\n");
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log(" iopadmap [options] [selection]\n");
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log("\n");
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log("Map module inputs/outputs to PAD cells from a library. This pass\n");
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log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
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log("the resulting cells to more sophisticated PAD cells.\n");
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log("\n");
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log(" -inpad <celltype> <portname>\n");
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log(" Map module input ports to the given cell type with\n");
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log(" the given port name.\n");
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log("\n");
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log(" -outpad <celltype> <portname>\n");
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log(" -inoutpad <celltype> <portname>\n");
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log(" Similar to -inpad, but for output and inout ports.\n");
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log("\n");
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log(" -widthparam <param_name>\n");
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log(" Use the specified parameter name to set the port width.\n");
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log("\n");
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log(" -nameparam <param_name>\n");
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log(" Use the specified parameter to set the port name.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
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std::string inpad_celltype, inpad_portname;
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std::string outpad_celltype, outpad_portname;
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std::string inoutpad_celltype, inoutpad_portname;
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std::string widthparam, nameparam;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-inpad" && argidx+2 < args.size()) {
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inpad_celltype = args[++argidx];
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inpad_portname = args[++argidx];
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continue;
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}
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if (arg == "-outpad" && argidx+2 < args.size()) {
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outpad_celltype = args[++argidx];
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outpad_portname = args[++argidx];
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continue;
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}
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if (arg == "-inoutpad" && argidx+2 < args.size()) {
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inoutpad_celltype = args[++argidx];
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inoutpad_portname = args[++argidx];
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continue;
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}
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if (arg == "-widthparam" && argidx+1 < args.size()) {
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widthparam = args[++argidx];
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continue;
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}
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if (arg == "-nameparam" && argidx+1 < args.size()) {
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nameparam = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &it : design->modules)
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{
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RTLIL::Module *module = it.second;
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if (!design->selected(module))
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continue;
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for (auto &it2 : module->wires)
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{
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RTLIL::Wire *wire = it2.second;
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if (!wire->port_id || !design->selected(module, wire))
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continue;
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std::string celltype, portname;
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if (wire->port_input && !wire->port_output) {
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if (inpad_celltype.empty()) {
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log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = inpad_celltype;
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portname = inpad_portname;
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} else
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if (!wire->port_input && wire->port_output) {
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if (outpad_celltype.empty()) {
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log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = outpad_celltype;
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portname = outpad_portname;
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} else
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if (wire->port_input && wire->port_output) {
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if (inoutpad_celltype.empty()) {
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log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = inoutpad_celltype;
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portname = inoutpad_portname;
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} else
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log_abort();
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if (wire->width != 1 && widthparam.empty()) {
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log("Don't map multi-bit port %s.%s: Missing option -widthparam.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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log("Mapping port %s.%s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = RTLIL::escape_id(celltype);
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cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
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if (!widthparam.empty())
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cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
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if (!nameparam.empty())
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cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
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cell->attributes["\\keep"] = RTLIL::Const();
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module->add(cell);
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wire->port_id = 0;
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wire->port_input = false;
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wire->port_output = false;
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}
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module->fixup_ports();
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}
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}
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} IopadmapPass;
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