mirror of https://github.com/YosysHQ/yosys.git
flowmap: clean up terminology.
* "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
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@ -769,7 +769,7 @@ struct FlowmapWorker
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}
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}
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int pack_luts()
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int map_luts()
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{
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pool<RTLIL::SigBit> worklist = outputs;
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while (!worklist.empty())
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@ -784,12 +784,12 @@ struct FlowmapWorker
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int depth = 0;
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for (auto label : labels)
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depth = max(depth, label.second);
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log("Solved to %d LUTs with maximum depth %d.\n", (int)lut_nodes.size(), depth);
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log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
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if (debug)
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{
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dump_dot_lut_graph("flowmap-packed.dot", GraphMode::Label);
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log("Dumped packed graph to `flowmap-packed.dot`.\n");
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dump_dot_lut_graph("flowmap-mapped.dot", GraphMode::Label);
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log("Dumped mapped graph to `flowmap-mapped.dot`.\n");
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}
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return depth;
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@ -1196,6 +1196,8 @@ struct FlowmapWorker
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bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
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{
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size_t initial_count = lut_nodes.size();
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for (auto node : lut_nodes)
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{
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lut_slacks[node] = depth_bound - (lut_depths[node] + lut_altitudes[node]);
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@ -1214,7 +1216,7 @@ struct FlowmapWorker
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if (potentials.empty())
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{
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log(" Relaxed to %d LUTs.\n", (int)lut_nodes.size());
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log(" Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
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if (!first && break_num == 1)
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{
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log(" Design fully relaxed.\n");
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@ -1338,7 +1340,7 @@ struct FlowmapWorker
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}
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}
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void map_cells(int minlut)
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void pack_cells(int minlut)
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{
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ConstEval ce(module);
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for (auto input_node : inputs)
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@ -1351,15 +1353,15 @@ struct FlowmapWorker
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{
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auto origin = node_origins[node];
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if (origin.cell->getPort(origin.port).size() == 1)
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log("Mapping %s.%s.%s (%s).\n",
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log("Packing %s.%s.%s (%s).\n",
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log_id(module), log_id(origin.cell), origin.port.c_str(), log_signal(node));
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else
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log("Mapping %s.%s.%s [%d] (%s).\n",
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log("Packing %s.%s.%s [%d] (%s).\n",
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log_id(module), log_id(origin.cell), origin.port.c_str(), origin.offset, log_signal(node));
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}
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else
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{
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log("Mapping %s.%s.\n", log_id(module), log_signal(node));
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log("Packing %s.%s.\n", log_id(module), log_signal(node));
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}
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for (auto gate_node : lut_gates[node])
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@ -1417,9 +1419,9 @@ struct FlowmapWorker
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lut_area += lut_table.size();
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if ((int)input_nodes.size() >= minlut)
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log(" Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
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log(" Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
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else
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log(" Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", (int)input_nodes.size(), log_id(module), log_id(lut), minlut);
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log(" Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
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}
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for (auto node : mapped_nodes)
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@ -1440,7 +1442,7 @@ struct FlowmapWorker
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log("Labeling cells.\n");
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discover_nodes(cell_types);
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label_nodes();
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int depth = pack_luts();
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int depth = map_luts();
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if (relax)
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{
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@ -1450,8 +1452,8 @@ struct FlowmapWorker
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}
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log("\n");
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log("Mapping cells.\n");
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map_cells(minlut);
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log("Packing cells.\n");
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pack_cells(minlut);
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}
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};
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@ -1603,9 +1605,8 @@ struct FlowmapPass : public Pass {
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}
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log("\n");
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log("Mapped %d LUTs.\n", lut_count);
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log("Packed %d cells; duplicated %d cells.\n", packed_count, packed_count - gate_count);
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log("Solution has %.1f%% area overhead.\n", (lut_area - gate_area) * 100.0 / gate_area);
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log("Packed %d cells (%d of them duplicated) into %d LUTs.\n", packed_count, packed_count - gate_count, lut_count);
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log("Solution takes %.1f%% of original gate area.\n", lut_area * 100.0 / gate_area);
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}
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} FlowmapPass;
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