mirror of https://github.com/YosysHQ/yosys.git
Be slightly less aggressive in "deminout" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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25c5002f83
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675a44b41a
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@ -57,7 +57,7 @@ struct DeminoutPass : public Pass {
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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pool<SigBit> bits_written, bits_used, bits_inout;
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pool<SigBit> bits_written, bits_used, bits_inout, bits_tribuf;
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dict<SigBit, int> bits_numports;
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for (auto wire : module->wires())
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@ -82,6 +82,25 @@ struct DeminoutPass : public Pass {
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if (cellport_in)
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for (auto bit : sigmap(conn.second))
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bits_used.insert(bit);
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if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_"))
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{
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bool tribuf = (cell->type == "$_TBUF_");
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if (!tribuf) {
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for (auto &c : cell->connections()) {
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if (!c.first.in("\\A", "\\B"))
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continue;
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for (auto b : sigmap(c.second))
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if (b == State::Sz)
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tribuf = true;
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}
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}
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if (tribuf)
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for (auto bit : sigmap(conn.second))
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bits_tribuf.insert(bit);
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}
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}
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for (auto wire : module->selected_wires())
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@ -95,10 +114,15 @@ struct DeminoutPass : public Pass {
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if (bits_numports[bit] > 1 || bits_inout.count(bit))
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new_input = true, new_output = true;
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if (bits_written.count(bit))
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if (bits_written.count(bit)) {
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new_output = true;
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else if (bits_used.count(bit))
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new_input = true;
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if (bits_tribuf.count(bit))
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goto tribuf_bit;
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} else {
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tribuf_bit:
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if (bits_used.count(bit))
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new_input = true;
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}
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}
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if (new_input != new_output) {
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