mirror of https://github.com/YosysHQ/yosys.git
Progress in "share" pass
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@ -27,7 +27,9 @@
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struct ShareWorkerConfig
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{
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bool opt_all;
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bool opt_force;
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bool opt_aggressive;
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bool opt_fast;
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};
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struct ShareWorker
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@ -56,7 +58,7 @@ struct ShareWorker
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if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
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continue;
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if (config.opt_all) {
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if (config.opt_force) {
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candidates.push_back(cell);
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continue;
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}
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@ -68,13 +70,19 @@ struct ShareWorker
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}
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if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
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if (cell->parameters.at("\\Y_WIDTH").as_int() > 4)
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 4)
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candidates.push_back(cell);
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continue;
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}
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if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
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if (cell->parameters.at("\\Y_WIDTH").as_int() > 8)
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 8)
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candidates.push_back(cell);
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continue;
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}
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if (cell->type == "$add" || cell->type == "$sub") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 10)
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candidates.push_back(cell);
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continue;
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}
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@ -109,7 +117,7 @@ struct ShareWorker
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return true;
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}
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if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" ||
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if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" ||
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c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
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{
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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@ -118,17 +126,20 @@ struct ShareWorker
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if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
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return false;
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
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if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
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if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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}
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return true;
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}
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@ -365,10 +376,15 @@ struct ShareWorker
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4)
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continue;
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// log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type));
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satgen.importCell(pbit.cell);
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sat_cells.insert(pbit.cell);
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}
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if (config.opt_fast && sat_cells.size() > 100)
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break;
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}
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all_ctrl_signals.sort_and_unify();
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@ -409,26 +425,47 @@ struct SharePass : public Pass {
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log("This pass merges shareable resources into a single resource. A SAT solver\n");
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log("is used to determine if two resources are share-able.\n");
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log("\n");
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log(" -all\n");
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log(" -force\n");
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log(" Per default the selection of cells that is considered for sharing is\n");
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log(" narrowed using some built-in heuristics. With this option all selected\n");
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log(" narrowed using a list of cell types. With this option all selected\n");
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log(" cells are considered for resource sharing.\n");
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log("\n");
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log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n");
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log(" state must be selected!\n");
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log("\n");
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log(" -aggressive\n");
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log(" Per default some heuristics are used to reduce the number of cells\n");
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log(" considered for resource sharing to only large resources. This options\n");
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log(" turns this heuristics off, resulting in much more cells being considered\n");
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log(" for resource sharing.\n");
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log("\n");
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log(" -fast\n");
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log(" Only consider comparable primitive control logic in SAT solving, resulting\n");
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log(" in much easier SAT problems at the cost of maybe missing some oportunities\n");
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log(" for resource sharing.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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ShareWorkerConfig config;
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config.opt_all = false;
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config.opt_force = false;
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config.opt_aggressive = false;
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config.opt_fast = false;
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log_header("Executing SHARE pass (SAT-based resource sharing).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-all") {
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config.opt_all = true;
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if (args[argidx] == "-force") {
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config.opt_force = true;
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continue;
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}
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if (args[argidx] == "-aggressive") {
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config.opt_aggressive = true;
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continue;
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}
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if (args[argidx] == "-fast") {
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config.opt_fast = true;
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continue;
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}
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break;
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