mirror of https://github.com/YosysHQ/yosys.git
Fixed techmap processes error msg
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@ -159,9 +159,10 @@ struct TechmapWorker
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void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
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{
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if (tpl->processes.size() != 0) {
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log("Technology map yielded processes:\n");
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log("Technology map yielded processes:");
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for (auto &it : tpl->processes)
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log(" %s",RTLIL::id2cstr(it.first));
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log(" %s",RTLIL::id2cstr(it.first));
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log("\n");
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if (autoproc_mode) {
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Pass::call_on_module(tpl->design, tpl, "proc");
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log_assert(GetSize(tpl->processes) == 0);
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