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Added sequential solving support to sat_solve

This commit is contained in:
Clifford Wolf 2013-06-09 13:35:46 +02:00
parent 6f330f0132
commit 0efde13775
3 changed files with 261 additions and 93 deletions
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81
kernel/satgen.h
View File

@ -38,6 +38,7 @@ struct SatGen
RTLIL::Design *design;
SigMap *sigmap;
std::string prefix;
SigPool initial_signals;
SatGen(ezSAT *ez, RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string()) :
ez(ez), design(design), sigmap(sigmap), prefix(prefix)
@ -51,8 +52,9 @@ struct SatGen
this->prefix = prefix;
}
std::vector<int> importSigSpec(RTLIL::SigSpec &sig)
std::vector<int> importSigSpec(RTLIL::SigSpec &sig, int timestep = -1)
{
assert(timestep < 0 || timestep > 0);
RTLIL::SigSpec s = sig;
sigmap->apply(s);
s.expand();
@ -61,11 +63,14 @@ struct SatGen
vec.reserve(s.chunks.size());
for (auto &c : s.chunks)
if (c.wire == NULL)
if (c.wire == NULL) {
vec.push_back(c.data.as_bool() ? ez->TRUE : ez->FALSE);
else
vec.push_back(ez->literal(prefix + stringf(c.wire->width == 1 ?
"%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset)));
} else {
std::string name = prefix;
name += timestep == -1 ? "" : stringf("@%d:", timestep);
name += stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset);
vec.push_back(ez->literal(name));
}
return vec;
}
@ -89,14 +94,14 @@ struct SatGen
vec_y.push_back(ez->literal());
}
bool importCell(RTLIL::Cell *cell)
bool importCell(RTLIL::Cell *cell, int timestep = -1)
{
if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_" ||
cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
cell->type == "$add" || cell->type == "$sub") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
extendSignalWidth(a, b, y, cell);
if (cell->type == "$and" || cell->type == "$_AND_")
ez->assume(ez->vec_eq(ez->vec_and(a, b), y));
@ -114,26 +119,26 @@ struct SatGen
}
if (cell->type == "$_INV_" || cell->type == "$not") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
ez->assume(ez->vec_eq(ez->vec_not(a), y));
return true;
}
if (cell->type == "$_MUX_" || cell->type == "$mux") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
std::vector<int> s = importSigSpec(cell->connections.at("\\S"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> s = importSigSpec(cell->connections.at("\\S"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), y));
return true;
}
if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
std::vector<int> s = importSigSpec(cell->connections.at("\\S"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> s = importSigSpec(cell->connections.at("\\S"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
std::vector<int> tmp = a;
for (size_t i = 0; i < s.size(); i++) {
std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
@ -146,8 +151,8 @@ struct SatGen
}
if (cell->type == "$pos" || cell->type == "$neg") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
if (cell->type == "$pos") {
ez->assume(ez->vec_eq(a, y));
} else {
@ -159,8 +164,8 @@ struct SatGen
if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
if (cell->type == "$reduce_and")
ez->SET(ez->expression(ez->OpAnd, a), y.at(0));
if (cell->type == "$reduce_or" || cell->type == "$reduce_bool")
@ -177,9 +182,9 @@ struct SatGen
}
if (cell->type == "$logic_and" || cell->type == "$logic_or") {
int a = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\A")));
int b = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\B")));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
int a = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\A"), timestep));
int b = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\B"), timestep));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
if (cell->type == "$logic_and")
ez->SET(ez->expression(ez->OpAnd, a, b), y.at(0));
else
@ -191,9 +196,9 @@ struct SatGen
if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$ge" || cell->type == "$gt") {
bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
extendSignalWidth(a, b, cell);
if (cell->type == "$lt")
ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), y.at(0));
@ -213,9 +218,9 @@ struct SatGen
}
if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
char shift_left = cell->type == "$shl" || cell->type == "$sshl";
bool sign_extend = cell->type == "$sshr";
while (y.size() < a.size())
@ -234,7 +239,19 @@ struct SatGen
return true;
}
if (timestep > 0 && (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")) {
if (timestep == 1) {
initial_signals.add((*sigmap)(cell->connections.at("\\Q")));
} else {
std::vector<int> d = importSigSpec(cell->connections.at("\\D"), timestep-1);
std::vector<int> q = importSigSpec(cell->connections.at("\\Q"), timestep);
ez->assume(ez->vec_eq(d, q));
}
return true;
}
// Unsupported internal cell types: $mul $div $mod $pow
// .. and all sequential cells except $dff and $_DFF_[NP]_
return false;
}
};

1
passes/sat/example.ys
View File

@ -4,3 +4,4 @@ sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
sat_solve -set y 1'b1 example004
sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004

272
passes/sat/sat_solve.cc
View File

@ -130,12 +130,25 @@ struct SatSolvePass : public Pass {
log(" show the model for the specified signal. if no -show option is\n");
log(" passed then a set of signals to be shown is automatically selected.\n");
log("\n");
log("The following options can be used to set up a sequential problem:\n");
log("\n");
log(" -seq <N>\n");
log(" set up a sequential problem with <N> time steps. The steps will\n");
log(" be numbered from 1 to N.\n");
log("\n");
log(" -set-at <N> <signal> <value>\n");
log(" -unset-at <N> <signal>\n");
log(" set or unset the specified signal to the specified value in the\n");
log(" given timestep. this has priority over a -set for the same signal.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
std::vector<std::pair<std::string, std::string>> sets;
std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
std::map<int, std::vector<std::string>> unsets_at;
std::vector<std::string> shows;
int loopcount = 0;
int loopcount = 0, seq_len = 0;
log_header("Executing SAT_SOLVE pass (solving SAT problems in the circuit).\n");
@ -155,6 +168,23 @@ struct SatSolvePass : public Pass {
sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
continue;
}
if (args[argidx] == "-seq" && argidx+1 < args.size()) {
seq_len = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-set-at" && argidx+3 < args.size()) {
int timestep = atoi(args[++argidx].c_str());
std::string lhs = args[++argidx].c_str();
std::string rhs = args[++argidx].c_str();
sets_at[timestep].push_back(std::pair<std::string, std::string>(lhs, rhs));
continue;
}
if (args[argidx] == "-unset-at" && argidx+2 < args.size()) {
int timestep = atoi(args[++argidx].c_str());
std::string lhs = args[++argidx].c_str();
unsets_at[timestep].push_back(lhs);
continue;
}
if (args[argidx] == "-show" && argidx+1 < args.size()) {
shows.push_back(args[++argidx]);
continue;
@ -186,47 +216,119 @@ struct SatSolvePass : public Pass {
std::map<RTLIL::Cell*,RTLIL::SigSpec> show_driven;
CellTypes ct(design);
for (auto &s : sets)
for (int timestep = -1; timestep <= seq_len; timestep++)
{
RTLIL::SigSpec lhs, rhs;
// set timestep=-1 for non-seq problems and timestep=1:N for seq problems
if ((timestep == -1 && seq_len > 0) || timestep == 0)
continue;
if (!parse_sigstr(lhs, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
if (!parse_sigstr(rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
if (timestep > 0)
log ("\nSetting up time step %d:\n", timestep);
else
log ("\nSetting up SAT problem:\n");
if (lhs.width != rhs.width)
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
RTLIL::SigSpec big_lhs, big_rhs;
log("Import constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
for (auto &s : sets)
{
RTLIL::SigSpec lhs, rhs;
std::vector<int> lhs_vec = satgen.importSigSpec(lhs);
std::vector<int> rhs_vec = satgen.importSigSpec(rhs);
if (!parse_sigstr(lhs, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
if (!parse_sigstr(rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
if (lhs.width != rhs.width)
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
big_lhs.append(lhs);
big_rhs.append(rhs);
}
for (auto &s : sets_at[timestep])
{
RTLIL::SigSpec lhs, rhs;
if (!parse_sigstr(lhs, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
if (!parse_sigstr(rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
if (lhs.width != rhs.width)
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
log("Import set-constraint for timestep: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
big_lhs.append(lhs);
big_rhs.append(rhs);
}
for (auto &s : unsets_at[timestep])
{
RTLIL::SigSpec lhs;
if (!parse_sigstr(lhs, module, s))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str());
show_signal_pool.add(sigmap(lhs));
log("Import unset-constraint for timestep: %s\n", log_signal(lhs));
big_lhs.remove2(lhs, &big_rhs);
}
log("Final constraint equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
std::vector<int> lhs_vec = satgen.importSigSpec(big_lhs, timestep);
std::vector<int> rhs_vec = satgen.importSigSpec(big_rhs, timestep);
ez.assume(ez.vec_eq(lhs_vec, rhs_vec));
int import_cell_counter = 0;
for (auto &c : module->cells)
if (design->selected(module, c.second) && ct.cell_known(c.second->type)) {
// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
if (satgen.importCell(c.second, timestep)) {
for (auto &p : c.second->connections)
if (ct.cell_output(c.second->type, p.first))
show_drivers.insert(sigmap(p.second), c.second);
else
show_driven[c.second].append(sigmap(p.second));
import_cell_counter++;
} else
log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
}
log("Imported %d cells to SAT database.\n", import_cell_counter);
}
int import_cell_counter = 0;
for (auto &c : module->cells)
if (design->selected(module, c.second) && ct.cell_known(c.second->type)) {
// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
if (satgen.importCell(c.second)) {
for (auto &p : c.second->connections)
if (ct.cell_output(c.second->type, p.first))
show_drivers.insert(sigmap(p.second), c.second);
else
show_driven[c.second].append(sigmap(p.second));
import_cell_counter++;
} else
log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
struct ModelBlockInfo {
int timestep, offset, width;
std::string description;
bool operator < (const ModelBlockInfo &other) const {
if (timestep != other.timestep)
return timestep < other.timestep;
if (description != other.description)
return description < other.description;
if (offset != other.offset)
return offset < other.offset;
if (width != other.width)
return width < other.width;
return false;
}
log("Imported %d cells to SAT database.\n", import_cell_counter);
};
RTLIL::SigSpec modelSig;
std::vector<int> modelExpressions;
std::vector<bool> modelValues;
std::set<ModelBlockInfo> modelInfo;
// Add "normal" show signals for every timestep
RTLIL::SigSpec modelSig;
if (shows.size() == 0) {
SigPool handled_signals, final_signals;
@ -256,52 +358,100 @@ struct SatSolvePass : public Pass {
}
}
modelSig.expand();
modelSig.sort_and_unify();
// log("Model signals: %s\n", log_signal(modelSig));
for (auto &c : modelSig.chunks)
if (c.wire != NULL) {
ModelBlockInfo info;
RTLIL::SigSpec chunksig = c;
std::vector<int> vec = satgen.importSigSpec(chunksig);
log_assert(vec.size() == 1);
modelExpressions.push_back(vec[0]);
info.width = chunksig.width;
info.description = log_signal(chunksig);
for (int timestep = -1; timestep <= seq_len; timestep++) {
if ((timestep == -1 && seq_len > 0) || timestep == 0)
continue;
std::vector<int> vec = satgen.importSigSpec(chunksig, timestep);
info.timestep = timestep;
info.offset = modelExpressions.size();
modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
modelInfo.insert(info);
}
}
// Add zero step signals as collected by satgen
modelSig = satgen.initial_signals.export_all();
for (auto &c : modelSig.chunks)
if (c.wire != NULL) {
ModelBlockInfo info;
RTLIL::SigSpec chunksig = c;
info.timestep = 0;
info.offset = modelExpressions.size();
info.width = chunksig.width;
info.description = log_signal(chunksig);
std::vector<int> vec = satgen.importSigSpec(chunksig, 1);
modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
modelInfo.insert(info);
}
#if 0
// print CNF for debugging
ez.printDIMACS(stdout, true);
#endif
rerun_solver:
log("Solving problem with %d variables and %d clauses..\n", ez.numCnfVariables(), ez.numCnfClauses());
log("\nSolving problem with %d variables and %d clauses..\n", ez.numCnfVariables(), ez.numCnfClauses());
if (ez.solve(modelExpressions, modelValues))
{
log("SAT solving finished - model found:\n\n");
log("SAT solving finished - model found:\n");
log("\n");
int modelIdx = 0;
int maxModelName = 10;
int maxModelWidth = 10;
modelSig.optimize();
for (auto &c : modelSig.chunks)
if (c.wire != NULL) {
maxModelName = std::max(maxModelName, int(c.wire->name.size()));
maxModelWidth = std::max(maxModelWidth, c.width);
}
const char *hline = "--------------------------------------------------------";
log(" %-*s %10s %10s %*s\n", maxModelName+10, "Signal Name", "Dec", "Hex", maxModelWidth+5, "Bin");
log(" %*.*s %10.10s %10.10s %*.*s\n", maxModelName+10, maxModelName+10,
hline, hline, hline, maxModelWidth+5, maxModelWidth+5, hline);
for (auto &c : modelSig.chunks) {
if (c.wire == NULL)
continue;
RTLIL::Const value;
for (int i = 0; i < c.width; i++)
value.bits.push_back(modelValues.at(modelIdx+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (c.width <= 32)
log(" %-*s %10d %10x %*s\n", maxModelName+10, log_signal(c), value.as_int(), value.as_int(), maxModelWidth+5, value.as_string().c_str());
else
log(" %-*s %10s %10s %*s\n", maxModelName+10, log_signal(c), "--", "--", maxModelWidth+5, value.as_string().c_str());
modelIdx += c.width;
for (auto &info : modelInfo) {
maxModelName = std::max(maxModelName, int(info.description.size()));
maxModelWidth = std::max(maxModelWidth, info.width);
}
int last_timestep = -2;
for (auto &info : modelInfo)
{
RTLIL::Const value;
for (int i = 0; i < info.width; i++)
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (info.timestep != last_timestep) {
const char *hline = "--------------------------------------------------------";
if (last_timestep == -2) {
log(seq_len > 0 ? " Time " : " ");
log("%-*s %10s %10s %*s\n", maxModelName+10, "Signal Name", "Dec", "Hex", maxModelWidth+5, "Bin");
}
log(seq_len > 0 ? " ---- " : " ");
log("%*.*s %10.10s %10.10s %*.*s\n", maxModelName+10, maxModelName+10,
hline, hline, hline, maxModelWidth+5, maxModelWidth+5, hline);
last_timestep = info.timestep;
}
if (seq_len > 0) {
if (info.timestep > 0)
log(" %4d ", info.timestep);
else
log(" init ");
} else
log(" ");
if (info.width <= 32)
log("%-*s %10d %10x %*s\n", maxModelName+10, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+5, value.as_string().c_str());
else
log("%-*s %10s %10s %*s\n", maxModelName+10, info.description.c_str(), "--", "--", maxModelWidth+5, value.as_string().c_str());
}
if (last_timestep == -2)
log(" no model variables selected for display.\n");
if (loopcount != 0) {
log("\n");
std::vector<int> clause;
for (size_t i = 0; i < modelExpressions.size(); i++)
clause.push_back(modelValues.at(i) ? ez.NOT(modelExpressions.at(i)) : modelExpressions.at(i));