mirror of https://github.com/YosysHQ/yosys.git
Fixed various VS warnings
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85572b05e5
commit
84ffe04075
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@ -2457,7 +2457,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
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}
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log_assert(block != NULL);
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log_assert(variables.count(str));
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log_assert(variables.count(str) != 0);
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while (!block->children.empty())
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{
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@ -64,7 +64,7 @@ int gettimeofday(struct timeval *tv, struct timezone *tz)
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counter.QuadPart *= 1000000;
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counter.QuadPart /= freq.QuadPart;
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tv->tv_sec = counter.QuadPart / 1000000;
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tv->tv_sec = long(counter.QuadPart / 1000000);
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tv->tv_usec = counter.QuadPart % 1000000;
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return 0;
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@ -1778,7 +1778,7 @@ const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() cons
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bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
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{
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return parameters.count(paramname);
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return parameters.count(paramname) != 0;
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}
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void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
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@ -3041,7 +3041,7 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R
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if (lhs.chunks_.size() == 1) {
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char *p = (char*)str.c_str(), *endptr;
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long long int val = strtoll(p, &endptr, 10);
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long int val = strtol(p, &endptr, 10);
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if (endptr && endptr != p && *endptr == 0) {
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sig = RTLIL::SigSpec(val, lhs.width_);
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cover("kernel.rtlil.sigspec.parse.rhs_dec");
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@ -231,7 +231,7 @@ std::string make_temp_file(std::string template_str)
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while (1) {
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for (int i = 0; i < 6; i++) {
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static std::string y = "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ";
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static uint32_t x = 314159265 ^ time(NULL);
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static uint32_t x = 314159265 ^ uint32_t(time(NULL));
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x ^= x << 13, x ^= x >> 17, x ^= x << 5;
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template_str[pos+i] = y[x % y.size()];
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}
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@ -1118,7 +1118,7 @@ int64_t ezSAT::vec_model_get_signed(const std::vector<int> &modelExpressions, co
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for (int i = 0; i < 64; i++) {
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int j = i < int(vec1.size()) ? i : vec1.size()-1;
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if (modelMap.at(vec1[j]))
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value |= 1 << i;
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value |= int64_t(1) << i;
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}
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return value;
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}
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@ -1132,7 +1132,7 @@ uint64_t ezSAT::vec_model_get_unsigned(const std::vector<int> &modelExpressions,
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modelMap[modelExpressions[i]] = modelValues[i];
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for (int i = 0; i < int(vec1.size()); i++)
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if (modelMap.at(vec1[i]))
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value |= 1 << i;
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value |= uint64_t(1) << i;
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return value;
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}
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@ -112,7 +112,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo
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if (regs.check_any(s1) != regs.check_any(s2))
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return regs.check_any(s2);
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if (direct_wires.count(w1) != direct_wires.count(w2))
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return direct_wires.count(w2);
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return direct_wires.count(w2) != 0;
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if (conns.check_any(s1) != conns.check_any(s2))
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return conns.check_any(s2);
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}
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@ -747,7 +747,7 @@ struct ShareWorker
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forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
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}
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log_assert(recursion_state.count(cell));
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log_assert(recursion_state.count(cell) != 0);
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recursion_state.erase(cell);
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return forbidden_controls_cache[cell];
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@ -862,7 +862,7 @@ struct ShareWorker
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activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end());
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}
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log_assert(recursion_state.count(cell));
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log_assert(recursion_state.count(cell) != 0);
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recursion_state.erase(cell);
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optimize_activation_patterns(activation_patterns_cache[cell]);
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@ -108,7 +108,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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float best_cell_area = 0;
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double best_cell_area = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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@ -144,7 +144,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
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this_cell_ports[cell_rst_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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float area = 0;
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double area = 0;
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LibertyAst *ar = cell->find("area");
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if (ar != NULL && !ar->value.empty())
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area = atof(ar->value.c_str());
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@ -204,7 +204,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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float best_cell_area = 0;
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double best_cell_area = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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@ -236,7 +236,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
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this_cell_ports[cell_clr_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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float area = 0;
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double area = 0;
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LibertyAst *ar = cell->find("area");
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if (ar != NULL && !ar->value.empty())
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area = atof(ar->value.c_str());
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