mirror of https://github.com/YosysHQ/yosys.git
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
This commit is contained in:
parent
926fa61119
commit
7f52c18a22
|
@ -160,6 +160,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
|
|||
|
||||
sig_rd_clk_enable.optimize();
|
||||
sig_rd_clk_polarity.optimize();
|
||||
sig_rd_transparent.optimize();
|
||||
|
||||
assert(sig_rd_clk.width == rd_ports);
|
||||
assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());
|
||||
|
|
Loading…
Reference in New Issue