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Using simplemap mappers from techmap

This commit is contained in:
Clifford Wolf 2013-11-24 23:31:14 +01:00
parent 3ee33cbdaf
commit 76f7c10cfc
3 changed files with 104 additions and 742 deletions
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55
passes/techmap/simplemap.cc
View File

@ -25,6 +25,8 @@
#include <stdio.h>
#include <string.h>
extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\Y_WIDTH").as_int();
@ -448,6 +450,30 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers["$not"] = simplemap_not;
mappers["$pos"] = simplemap_pos;
mappers["$and"] = simplemap_bitop;
mappers["$or"] = simplemap_bitop;
mappers["$xor"] = simplemap_bitop;
mappers["$xnor"] = simplemap_bitop;
mappers["$reduce_and"] = simplemap_reduce;
mappers["$reduce_or"] = simplemap_reduce;
mappers["$reduce_xor"] = simplemap_reduce;
mappers["$reduce_xnor"] = simplemap_reduce;
mappers["$reduce_bool"] = simplemap_reduce;
mappers["$logic_not"] = simplemap_lognot;
mappers["$logic_and"] = simplemap_logbin;
mappers["$logic_or"] = simplemap_logbin;
mappers["$mux"] = simplemap_mux;
mappers["$sr"] = simplemap_sr;
mappers["$dff"] = simplemap_dff;
mappers["$dffsr"] = simplemap_dffsr;
mappers["$adff"] = simplemap_adff;
mappers["$dlatch"] = simplemap_dlatch;
}
struct SimplemapPass : public Pass {
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
virtual void help()
@ -470,41 +496,20 @@ struct SimplemapPass : public Pass {
log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
extra_args(args, 1, design);
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> supported_cells;
supported_cells["$not"] = simplemap_not;
supported_cells["$pos"] = simplemap_pos;
supported_cells["$and"] = simplemap_bitop;
supported_cells["$or"] = simplemap_bitop;
supported_cells["$xor"] = simplemap_bitop;
supported_cells["$xnor"] = simplemap_bitop;
supported_cells["$reduce_and"] = simplemap_reduce;
supported_cells["$reduce_or"] = simplemap_reduce;
supported_cells["$reduce_xor"] = simplemap_reduce;
supported_cells["$reduce_xnor"] = simplemap_reduce;
supported_cells["$reduce_bool"] = simplemap_reduce;
supported_cells["$logic_not"] = simplemap_lognot;
supported_cells["$logic_and"] = simplemap_logbin;
supported_cells["$logic_or"] = simplemap_logbin;
supported_cells["$mux"] = simplemap_mux;
supported_cells["$sr"] = simplemap_sr;
supported_cells["$dff"] = simplemap_dff;
supported_cells["$dffsr"] = simplemap_dffsr;
supported_cells["$adff"] = simplemap_adff;
supported_cells["$dlatch"] = simplemap_dlatch;
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
for (auto &mod_it : design->modules) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> delete_cells;
for (auto &cell_it : mod_it.second->cells) {
auto mapper = supported_cells[cell_it.second->type];
if (mapper == NULL)
if (mappers.count(cell_it.second->type) == 0)
continue;
if (!design->selected(mod_it.second, cell_it.second))
continue;
log("Mapping %s.%s (%s).\n", RTLIL::id2cstr(mod_it.first), RTLIL::id2cstr(cell_it.first), RTLIL::id2cstr(cell_it.second->type));
mapper(mod_it.second, cell_it.second);
mappers.at(cell_it.second->type)(mod_it.second, cell_it.second);
delete_cells.push_back(cell_it.second);
}
for (auto &it : delete_cells) {

37
passes/techmap/techmap.cc
View File

@ -27,6 +27,9 @@
#include "passes/techmap/stdcells.inc"
// see simplemap.cc
extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
static void apply_prefix(std::string prefix, std::string &id)
{
if (id[0] == '\\')
@ -47,6 +50,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
}
}
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
std::map<RTLIL::Module*, bool> techmap_do_cache;
@ -217,7 +221,20 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
RTLIL::Module *tpl = map->modules[tpl_name];
std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
if (!flatten_mode) {
if (!flatten_mode)
{
if (tpl->get_bool_attribute("\\techmap_simplemap")) {
log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
if (simplemap_mappers.count(cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
simplemap_mappers.at(cell->type)(module, cell);
module->cells.erase(cell->name);
delete cell;
cell = NULL;
did_something = true;
break;
}
for (auto conn : cell->connections) {
if (conn.first.substr(0, 1) == "$")
continue;
@ -386,11 +403,15 @@ struct TechmapPass : public Pass {
log(" '-ignore_redef' option set.\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute.\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n");
log("the module name will be used to match the cell.\n");
log("\n");
log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
log("\n");
log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
log("the mapping module to the techmap command. At the moment the following spoecial\n");
log("the mapping module to the techmap command. At the moment the following special\n");
log("wires are supported:\n");
log("\n");
log(" _TECHMAP_FAIL_\n");
@ -412,6 +433,13 @@ struct TechmapPass : public Pass {
log(" wire to start out as non-constant and evaluate to a constant value\n");
log(" during processing of other _TECHMAP_DO_* commands.\n");
log("\n");
log("In addition to this special wires, techmap also supports special parameters in\n");
log("modules in the map file:\n");
log("\n");
log(" _TECHMAP_CELLTYPE_\n");
log(" When a parameter with this name exists, it will be set to the type name\n");
log(" of the cell that matches the module.\n");
log("\n");
log("When a module in the map file has a parameter where the according cell in the\n");
log("design has a port, the module from the map file is only used if the port in\n");
log("the design is connected to a constant value. The parameter is then set to the\n");
@ -453,6 +481,8 @@ struct TechmapPass : public Pass {
}
extra_args(args, argidx, design);
simplemap_get_mappers(simplemap_mappers);
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
@ -500,6 +530,7 @@ struct TechmapPass : public Pass {
log("No more expansions possible.\n");
techmap_cache.clear();
techmap_do_cache.clear();
simplemap_mappers.clear();
delete map;
log_pop();
}

754
techlibs/common/stdcells.v
View File

@ -32,54 +32,14 @@
// --------------------------------------------------------
module \$not (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
\$_INV_ gate (
.A(A_buf[i]),
.Y(Y[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$not ;
endmodule
// --------------------------------------------------------
module \$pos (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
if (i < A_WIDTH) begin
assign Y[i] = A[i];
end else if (A_SIGNED) begin
assign Y[i] = A[A_WIDTH-1];
end else begin
assign Y[i] = 0;
end
end
endgenerate
(* techmap_simplemap *)
module \$pos ;
endmodule
// --------------------------------------------------------
@ -109,286 +69,57 @@ endmodule
// --------------------------------------------------------
module \$and (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
\$_AND_ gate (
.A(A_buf[i]),
.B(B_buf[i]),
.Y(Y[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$and ;
endmodule
// --------------------------------------------------------
module \$or (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
\$_OR_ gate (
.A(A_buf[i]),
.B(B_buf[i]),
.Y(Y[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$or ;
endmodule
// --------------------------------------------------------
module \$xor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
\$_XOR_ gate (
.A(A_buf[i]),
.B(B_buf[i]),
.Y(Y[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$xor ;
endmodule
// --------------------------------------------------------
module \$xnor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
wire tmp;
\$_XOR_ gate1 (
.A(A_buf[i]),
.B(B_buf[i]),
.Y(tmp)
);
\$_INV_ gate2 (
.A(tmp),
.Y(Y[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$xnor ;
endmodule
// --------------------------------------------------------
module \$reduce_and (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [A_WIDTH-1:0] buffer;
genvar i;
generate
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
\$_AND_ gate (
.A(A[i]),
.B(buffer[i-1]),
.Y(buffer[i])
);
end
endgenerate
assign buffer[0] = A[0];
assign Y = buffer[A_WIDTH-1];
(* techmap_simplemap *)
module \$reduce_and ;
endmodule
// --------------------------------------------------------
module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [A_WIDTH-1:0] buffer;
genvar i;
generate
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
\$_OR_ gate (
.A(A[i]),
.B(buffer[i-1]),
.Y(buffer[i])
);
end
endgenerate
assign buffer[0] = A[0];
assign Y = buffer[A_WIDTH-1];
(* techmap_simplemap *)
module \$reduce_or ;
endmodule
// --------------------------------------------------------
module \$reduce_xor (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [A_WIDTH-1:0] buffer;
genvar i;
generate
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
\$_XOR_ gate (
.A(A[i]),
.B(buffer[i-1]),
.Y(buffer[i])
);
end
endgenerate
assign buffer[0] = A[0];
assign Y = buffer[A_WIDTH-1];
(* techmap_simplemap *)
module \$reduce_xor ;
endmodule
// --------------------------------------------------------
module \$reduce_xnor (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [A_WIDTH-1:0] buffer;
genvar i;
generate
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
\$_XOR_ gate (
.A(A[i]),
.B(buffer[i-1]),
.Y(buffer[i])
);
end
endgenerate
assign buffer[0] = A[0];
\$_INV_ gate_inv (
.A(buffer[A_WIDTH-1]),
.Y(Y[0])
);
generate
if (Y_WIDTH > 1) begin:V
assign Y[Y_WIDTH-1:1] = 0;
end
endgenerate
(* techmap_simplemap *)
module \$reduce_xnor ;
endmodule
// --------------------------------------------------------
module \$reduce_bool (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [A_WIDTH-1:0] buffer;
genvar i;
generate
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
\$_OR_ gate (
.A(A[i]),
.B(buffer[i-1]),
.Y(buffer[i])
);
end
endgenerate
assign buffer[0] = A[0];
assign Y = buffer[A_WIDTH-1];
(* techmap_simplemap *)
module \$reduce_bool ;
endmodule
// --------------------------------------------------------
@ -1181,157 +912,26 @@ endmodule
// --------------------------------------------------------
****/
module \$logic_not (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire A_buf;
\$reduce_bool #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(1)
) A_logic (
.A(A),
.Y(A_buf)
);
\$_INV_ gate (
.A(A_buf),
.Y(Y[0])
);
generate
if (Y_WIDTH > 1) begin:V
assign Y[Y_WIDTH-1:1] = 0;
end
endgenerate
(* techmap_simplemap *)
module \$logic_not ;
endmodule
// --------------------------------------------------------
module \$logic_and (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire A_buf, B_buf;
\$reduce_bool #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(1)
) A_logic (
.A(A),
.Y(A_buf)
);
\$reduce_bool #(
.A_SIGNED(B_SIGNED),
.A_WIDTH(B_WIDTH),
.Y_WIDTH(1)
) B_logic (
.A(B),
.Y(B_buf)
);
\$_AND_ gate (
.A(A_buf),
.B(B_buf),
.Y(Y[0])
);
generate
if (Y_WIDTH > 1) begin:V
assign Y[Y_WIDTH-1:1] = 0;
end
endgenerate
(* techmap_simplemap *)
module \$logic_and ;
endmodule
// --------------------------------------------------------
module \$logic_or (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire A_buf, B_buf;
\$reduce_bool #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(1)
) A_logic (
.A(A),
.Y(A_buf)
);
\$reduce_bool #(
.A_SIGNED(B_SIGNED),
.A_WIDTH(B_WIDTH),
.Y_WIDTH(1)
) B_logic (
.A(B),
.Y(B_buf)
);
\$_OR_ gate (
.A(A_buf),
.B(B_buf),
.Y(Y[0])
);
generate
if (Y_WIDTH > 1) begin:V
assign Y[Y_WIDTH-1:1] = 0;
end
endgenerate
(* techmap_simplemap *)
module \$logic_or ;
endmodule
// --------------------------------------------------------
module \$mux (A, B, S, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
input S;
output [WIDTH-1:0] Y;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_MUX_ gate (
.A(A[i]),
.B(B[i]),
.S(S),
.Y(Y[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$mux ;
endmodule
// --------------------------------------------------------
@ -1410,306 +1010,32 @@ endmodule
// --------------------------------------------------------
module \$sr (SET, CLR, Q);
parameter WIDTH = 0;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input [WIDTH-1:0] SET, CLR;
output reg [WIDTH-1:0] Q;
genvar i;
generate
if (SET_POLARITY == 0 && CLR_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_SR_NN_ ff (
.S(SET[i]),
.R(CLR[i]),
.Q(Q[i])
);
end
if (SET_POLARITY == 0 && CLR_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_SR_NP_ ff (
.S(SET[i]),
.R(CLR[i]),
.Q(Q[i])
);
end
if (SET_POLARITY != 0 && CLR_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_SR_PN_ ff (
.S(SET[i]),
.R(CLR[i]),
.Q(Q[i])
);
end
if (SET_POLARITY != 0 && CLR_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_SR_PP_ ff (
.S(SET[i]),
.R(CLR[i]),
.Q(Q[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$sr ;
endmodule
// --------------------------------------------------------
module \$dff (CLK, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1'b1;
input CLK;
input [WIDTH-1:0] D;
output [WIDTH-1:0] Q;
genvar i;
generate
if (CLK_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFF_N_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK)
);
end
if (CLK_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFF_P_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK)
);
end
endgenerate
(* techmap_simplemap *)
module \$dff ;
endmodule
// --------------------------------------------------------
module \$adff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output [WIDTH-1:0] Q;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin:V
if (CLK_POLARITY == 0) begin:N
if (ARST_POLARITY == 0) begin:NN
if (ARST_VALUE[i] == 0) begin:NN0
\$_DFF_NN0_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end else begin:NN1
\$_DFF_NN1_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end
end else begin:NP
if (ARST_VALUE[i] == 0) begin:NP0
\$_DFF_NP0_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end else begin:NP1
\$_DFF_NP1_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end
end
end else begin:P
if (ARST_POLARITY == 0) begin:PN
if (ARST_VALUE[i] == 0) begin:PN0
\$_DFF_PN0_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end else begin:PN1
\$_DFF_PN1_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end
end else begin:PP
if (ARST_VALUE[i] == 0) begin:PP0
\$_DFF_PP0_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end else begin:PP1
\$_DFF_PP1_ ff (
.D(D[i]),
.Q(Q[i]),
.C(CLK),
.R(ARST)
);
end
end
end
end
endgenerate
(* techmap_simplemap *)
module \$adff ;
endmodule
// --------------------------------------------------------
module \$dffsr (CLK, SET, CLR, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input CLK;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
genvar i;
generate
if (CLK_POLARITY == 0 && SET_POLARITY == 0 && CLR_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_NNN_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY == 0 && SET_POLARITY == 0 && CLR_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_NNP_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY == 0 && SET_POLARITY != 0 && CLR_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_NPN_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY == 0 && SET_POLARITY != 0 && CLR_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_NPP_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY != 0 && SET_POLARITY == 0 && CLR_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_PNN_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY != 0 && SET_POLARITY == 0 && CLR_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_PNP_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY != 0 && SET_POLARITY != 0 && CLR_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_PPN_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
if (CLK_POLARITY != 0 && SET_POLARITY != 0 && CLR_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DFFSR_PPP_ ff (
.C(CLK),
.S(SET[i]),
.R(CLR[i]),
.D(D[i]),
.Q(Q[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$dffsr ;
endmodule
// --------------------------------------------------------
module \$dlatch (EN, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
input EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
genvar i;
generate
if (EN_POLARITY == 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DLATCH_N_ ff (
.E(EN),
.D(D[i]),
.Q(Q[i])
);
end
if (EN_POLARITY != 0)
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$_DLATCH_P_ ff (
.E(EN),
.D(D[i]),
.Q(Q[i])
);
end
endgenerate
(* techmap_simplemap *)
module \$dlatch ;
endmodule
// --------------------------------------------------------