riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Logic loop bugfix for "share" pass

This commit is contained in:
Clifford Wolf 2014-09-21 15:13:44 +02:00
parent b28be0759f
commit d6e2ace95b
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
passes/opt/share.cc
View File

@ -958,13 +958,17 @@ struct ShareWorker
for (auto bit : topo_sigmap(all_ctrl_signals))
for (auto c : topo_bit_drivers[bit])
topo_cell_drivers[cell].insert(c);
topo_cell_drivers[supercell].insert(c);
topo_cell_drivers[supercell].insert(topo_cell_drivers[cell].begin(), topo_cell_drivers[cell].end());
topo_cell_drivers[supercell].insert(topo_cell_drivers[other_cell].begin(), topo_cell_drivers[other_cell].end());
topo_cell_drivers[cell] = { supercell };
topo_cell_drivers[other_cell] = { supercell };
if (config.limit > 0)
config.limit--;
topo_cell_drivers[cell].insert(topo_cell_drivers[other_cell].begin(), topo_cell_drivers[other_cell].end());
topo_cell_drivers[other_cell] = topo_cell_drivers[cell];
break;
}
}