mirror of https://github.com/YosysHQ/yosys.git
Update more stuff to use get_src_attribute() and set_src_attribute()
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8dc6083de7
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@ -1643,7 +1643,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
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cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
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cell->setPort("\\A", sig_a); \
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cell->setPort("\\Y", sig_y); \
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if (!src.empty()) cell->attributes["\\src"] = src; \
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cell->set_src_attribute(src); \
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return cell; \
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} \
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RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \
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@ -55,19 +55,19 @@ struct AlumaccWorker
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RTLIL::SigSpec get_gt() {
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if (GetSize(cached_gt) == 0)
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cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->attributes["\\src"].decode_string());
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cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
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return cached_gt;
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}
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RTLIL::SigSpec get_eq() {
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if (GetSize(cached_eq) == 0)
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cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->attributes["\\src"].decode_string());
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cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->get_src_attribute());
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return cached_eq;
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}
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RTLIL::SigSpec get_ne() {
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if (GetSize(cached_ne) == 0)
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cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->attributes["\\src"].decode_string());
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cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
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return cached_ne;
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}
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@ -75,7 +75,7 @@ struct AlumaccWorker
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if (GetSize(cached_cf) == 0) {
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cached_cf = alu_cell->getPort("\\CO");
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log_assert(GetSize(cached_cf) >= 1);
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cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->attributes["\\src"].decode_string());
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cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
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}
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return cached_cf;
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}
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