mirror of https://github.com/YosysHQ/yosys.git
More hashtable finetuning
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@ -23,6 +23,8 @@
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#include <string>
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#include <vector>
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#define YOSYS_HASHTABLE_SIZE_FACTOR 3
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inline unsigned int mkhash(unsigned int a, unsigned int b) {
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return ((a << 5) + a) ^ b;
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}
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@ -81,8 +83,19 @@ struct hash_ptr_ops {
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}
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};
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struct hash_obj_ops {
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bool cmp(const void *a, const void *b) const {
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return a == b;
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}
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template<typename T>
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unsigned int hash(const T *a) const {
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return a->name.hash();
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}
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};
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inline int hashtable_size(int old_size)
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{
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// prime numbers, approx. in powers of two
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if (old_size < 53) return 53;
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if (old_size < 113) return 113;
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if (old_size < 251) return 251;
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@ -144,7 +157,9 @@ class dict
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entries.clear();
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counter = other.size();
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int new_size = hashtable_size(counter);
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * counter);
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hashtable.resize(new_size);
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new_size = new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1;
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entries.reserve(new_size);
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for (auto &it : other)
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@ -165,7 +180,6 @@ class dict
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{
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free_list = -1;
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hashtable.resize(entries.size());
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for (auto &h : hashtable)
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h = -1;
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@ -221,7 +235,9 @@ class dict
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if (free_list < 0)
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{
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int i = entries.size();
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entries.resize(hashtable_size(i));
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * entries.size());
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hashtable.resize(new_size);
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entries.resize(new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1);
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entries[i].udata = value;
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entries[i].set_next_used(0);
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counter++;
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@ -473,7 +489,9 @@ class pool
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entries.clear();
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counter = other.size();
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int new_size = hashtable_size(counter);
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * counter);
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hashtable.resize(new_size);
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new_size = new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1;
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entries.reserve(new_size);
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for (auto &it : other)
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@ -494,7 +512,6 @@ class pool
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{
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free_list = -1;
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hashtable.resize(entries.size());
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for (auto &h : hashtable)
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h = -1;
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@ -550,7 +567,9 @@ class pool
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if (free_list < 0)
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{
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int i = entries.size();
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entries.resize(hashtable_size(i));
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * entries.size());
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hashtable.resize(new_size);
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entries.resize(new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1);
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entries[i].key = key;
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entries[i].set_next_used(0);
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counter++;
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@ -1132,7 +1132,7 @@ namespace {
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struct DeleteWireWorker
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{
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RTLIL::Module *module;
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const pool<RTLIL::Wire*, hash_ptr_ops> *wires_p;
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const pool<RTLIL::Wire*, hash_obj_ops> *wires_p;
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void operator()(RTLIL::SigSpec &sig) {
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std::vector<RTLIL::SigChunk> chunks = sig;
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@ -1146,7 +1146,7 @@ namespace {
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};
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}
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void RTLIL::Module::remove(const pool<RTLIL::Wire*, hash_ptr_ops> &wires)
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void RTLIL::Module::remove(const pool<RTLIL::Wire*, hash_obj_ops> &wires)
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{
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log_assert(refcount_wires_ == 0);
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@ -708,6 +708,8 @@ struct RTLIL::Selection
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struct RTLIL::Monitor
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{
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RTLIL::IdString name;
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Monitor() { name = stringf("$%d", autoidx++); }
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virtual ~Monitor() { }
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virtual void notify_module_add(RTLIL::Module*) { }
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virtual void notify_module_del(RTLIL::Module*) { }
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@ -719,7 +721,7 @@ struct RTLIL::Monitor
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struct RTLIL::Design
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{
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pool<RTLIL::Monitor*, hash_ptr_ops> monitors;
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pool<RTLIL::Monitor*, hash_obj_ops> monitors;
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dict<std::string, std::string> scratchpad;
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int refcount_modules_;
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@ -806,7 +808,7 @@ protected:
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public:
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RTLIL::Design *design;
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pool<RTLIL::Monitor*, hash_ptr_ops> monitors;
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pool<RTLIL::Monitor*, hash_obj_ops> monitors;
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int refcount_wires_;
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int refcount_cells_;
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@ -860,7 +862,7 @@ public:
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RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
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// Removing wires is expensive. If you have to remove wires, remove them all at once.
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void remove(const pool<RTLIL::Wire*, hash_ptr_ops> &wires);
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void remove(const pool<RTLIL::Wire*, hash_obj_ops> &wires);
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void remove(RTLIL::Cell *cell);
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void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
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@ -149,6 +149,8 @@ void remove_directory(std::string dirname);
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template<typename T> int GetSize(const T &obj) { return obj.size(); }
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int GetSize(RTLIL::Wire *wire);
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extern int autoidx;
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YOSYS_NAMESPACE_END
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#include "kernel/log.h"
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@ -164,7 +166,6 @@ void yosys_shutdown();
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Tcl_Interp *yosys_get_tcl_interp();
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#endif
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extern int autoidx;
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extern RTLIL::Design *yosys_design;
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RTLIL::IdString new_id(std::string file, int line, std::string func);
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@ -91,8 +91,8 @@ struct DeletePass : public Pass {
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continue;
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}
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pool<RTLIL::Wire*, hash_ptr_ops> delete_wires;
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pool<RTLIL::Cell*, hash_ptr_ops> delete_cells;
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pool<RTLIL::Wire*, hash_obj_ops> delete_wires;
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pool<RTLIL::Cell*, hash_obj_ops> delete_cells;
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pool<RTLIL::IdString> delete_procs;
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pool<RTLIL::IdString> delete_mems;
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@ -176,7 +176,7 @@ struct SplitnetsPass : public Pass {
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module->rewrite_sigspecs(worker);
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pool<RTLIL::Wire*, hash_ptr_ops> delete_wires;
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pool<RTLIL::Wire*, hash_obj_ops> delete_wires;
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for (auto &it : worker.splitmap)
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delete_wires.insert(it.first);
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module->remove(delete_wires);
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@ -262,7 +262,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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}
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pool<RTLIL::Wire*, hash_ptr_ops> del_wires;
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pool<RTLIL::Wire*, hash_obj_ops> del_wires;
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int del_wires_count = 0;
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for (auto wire : maybe_del_wires)
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@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
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TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_ptr_ops> cell_to_inbit;
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_obj_ops> cell_to_inbit;
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dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->cells())
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@ -41,7 +41,7 @@ struct OptShareWorker
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CellTypes ct;
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int total_count;
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#ifdef USE_CELL_HASH_CACHE
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dict<const RTLIL::Cell*, std::string, hash_ptr_ops> cell_hash_cache;
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dict<const RTLIL::Cell*, std::string, hash_obj_ops> cell_hash_cache;
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#endif
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#ifdef USE_CELL_HASH_CACHE
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