mirror of https://github.com/YosysHQ/yosys.git
Fixed sharing of $memrd cells
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@ -708,6 +708,10 @@ struct ShareWorker
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if (c1->type == "$memrd")
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{
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RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
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RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
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RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
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if (addr1 != addr2)
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supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act));
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supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
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supercell_aux.insert(supercell);
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return supercell;
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