mirror of https://github.com/YosysHQ/yosys.git
Fixed ice40 handling of negclk RAM40
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6f9a6fd783
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@ -90,7 +90,7 @@ module \$__ICE40_RAM4K (
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (WCLK ),
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.WCLKN(WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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@ -119,7 +119,7 @@ module \$__ICE40_RAM4K (
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(RDATA),
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.RCLK (RCLK ),
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.RCLKN(RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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@ -152,11 +152,11 @@ module \$__ICE40_RAM4K (
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(RDATA),
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.RCLK (RCLK ),
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.RCLKN(RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (WCLK ),
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.WCLKN(WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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@ -473,7 +473,7 @@ endmodule
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module SB_RAM40_4KNR (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input [10:0] WADDR,
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@ -520,7 +520,7 @@ module SB_RAM40_4KNR (
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.INIT_F (INIT_F )
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) RAM (
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.RDATA(RDATA),
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.RCLK (~RCLK),
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.RCLK (~RCLKN),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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@ -537,7 +537,7 @@ module SB_RAM40_4KNW (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input WCLKN, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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@ -586,7 +586,7 @@ module SB_RAM40_4KNW (
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (~WCLK),
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.WCLK (~WCLKN),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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@ -597,9 +597,9 @@ endmodule
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module SB_RAM40_4KNRNW (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input WCLKN, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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@ -644,11 +644,11 @@ module SB_RAM40_4KNRNW (
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.INIT_F (INIT_F )
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) RAM (
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.RDATA(RDATA),
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.RCLK (~RCLK),
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.RCLK (~RCLKN),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (~WCLK),
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.WCLK (~WCLKN),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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