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Properly clean up unused "init" attributes

This commit is contained in:
Clifford Wolf 2015-08-18 13:50:15 +02:00
parent a7ab9172f9
commit f43815054e
2 changed files with 36 additions and 6 deletions
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20
passes/opt/opt_rmdff.cc
View File

@ -28,6 +28,15 @@ PRIVATE_NAMESPACE_BEGIN
SigMap assign_map, dff_init_map;
SigSet<RTLIL::Cell*> mux_drivers;
dict<SigBit, pool<SigBit>> init_attributes;
void remove_init_attr(SigSpec sig)
{
for (auto bit : assign_map(sig))
if (init_attributes.count(bit))
for (auto wbit : init_attributes.at(bit))
wbit.wire->attributes.at("\\init")[wbit.offset] = State::Sx;
}
bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
{
@ -52,6 +61,7 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
delete_dlatch:
log("Removing %s (%s) from module %s.\n", dlatch->name.c_str(), dlatch->type.c_str(), mod->name.c_str());
remove_init_attr(dlatch->getPort("\\Q"));
mod->remove(dlatch);
return true;
}
@ -145,7 +155,6 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
}
if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
log_dump(sig_q, sig_d);
mod->connect(sig_q, sig_d);
goto delete_dff;
}
@ -162,6 +171,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
delete_dff:
log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str());
remove_init_attr(dff->getPort("\\Q"));
mod->remove(dff);
return true;
}
@ -193,8 +203,14 @@ struct OptRmdffPass : public Pass {
assign_map.set(mod_it.second);
dff_init_map.set(mod_it.second);
for (auto &it : mod_it.second->wires_)
if (it.second->attributes.count("\\init") != 0)
if (it.second->attributes.count("\\init") != 0) {
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
for (int i = 0; i < GetSize(it.second); i++) {
SigBit wire_bit(it.second, i), mapped_bit = assign_map(wire_bit);
if (mapped_bit.wire)
init_attributes[mapped_bit].insert(wire_bit);
}
}
mux_drivers.clear();
std::vector<RTLIL::IdString> dff_list;

22
passes/techmap/dffinit.cc
View File

@ -63,16 +63,26 @@ struct DffinitPass : public Pass {
SigMap sigmap(module);
dict<SigBit, State> init_bits;
pool<SigBit> cleanup_bits;
pool<SigBit> used_bits;
for (auto wire : module->selected_wires())
for (auto wire : module->selected_wires()) {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
for (auto bit : sigmap(wire))
used_bits.insert(bit);
}
for (auto cell : module->selected_cells())
{
for (auto it : cell->connections())
if (!cell->known() || cell->input(it.first))
for (auto bit : sigmap(it.second))
used_bits.insert(bit);
if (ff_types.count(cell->type) == 0)
continue;
@ -104,11 +114,15 @@ struct DffinitPass : public Pass {
for (auto wire : module->selected_wires())
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
Const &value = wire->attributes.at("\\init");
bool do_cleanup = true;
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
if (cleanup_bits.count(sigmap(SigBit(wire, i))) == 0)
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (cleanup_bits.count(bit) || !used_bits.count(bit))
value[i] = State::Sx;
else if (value[i] != State::Sx)
do_cleanup = false;
}
if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
wire->attributes.erase("\\init");