mirror of https://github.com/YosysHQ/yosys.git
More write_xaiger cleanup
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4be417f6e1
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14e870d4c4
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@ -105,7 +105,7 @@ struct XAigerWriter
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return aig_map.at(bit);
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}
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XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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XAigerWriter(Module *module, bool zinit_mode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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@ -543,10 +543,6 @@ struct XAigerWriter
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ff_aig_map[bit] = 2*aig_m;
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}
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if (imode && input_bits.empty()) {
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aig_m++, aig_i++;
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}
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//if (zinit_mode)
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//{
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// for (auto it : ff_map) {
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@ -620,13 +616,9 @@ struct XAigerWriter
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aig_outputs.push_back(ff_aig_map.at(bit));
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}
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if (omode && output_bits.empty()) {
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aig_o++;
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aig_outputs.push_back(0);
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool omode)
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void write_aiger(std::ostream &f, bool ascii_mode)
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{
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int aig_obc = aig_o;
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int aig_obcj = aig_obc;
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@ -716,18 +708,15 @@ struct XAigerWriter
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#endif
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h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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};
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int num_outputs = output_bits.size();
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if (omode && num_outputs == 0)
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num_outputs = 1;
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write_h_buffer(1);
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log_debug("ciNum = %zu\n", input_bits.size() + ff_bits.size() + ci_bits.size());
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write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
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log_debug("coNum = %zu\n", num_outputs + ff_bits.size() + co_bits.size());
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write_h_buffer(num_outputs + ff_bits.size()+ co_bits.size());
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log_debug("coNum = %zu\n", output_bits.size() + ff_bits.size() + co_bits.size());
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write_h_buffer(output_bits.size() + ff_bits.size()+ co_bits.size());
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log_debug("piNum = %zu\n", input_bits.size() + ff_bits.size());
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write_h_buffer(input_bits.size()+ ff_bits.size());
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log_debug("poNum = %zu\n", num_outputs + ff_bits.size());
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write_h_buffer(num_outputs + ff_bits.size());
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log_debug("poNum = %zu\n", output_bits.size() + ff_bits.size());
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write_h_buffer(output_bits.size() + ff_bits.size());
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log_debug("boxNum = %zu\n", box_list.size());
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write_h_buffer(box_list.size());
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@ -859,8 +848,8 @@ struct XAigerWriter
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holes_module->design->selection_stack.pop_back();
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/, false /* omode */);
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XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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f << "a";
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std::string buffer_str = a_buffer.str();
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@ -879,7 +868,7 @@ struct XAigerWriter
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f << stringf("Generated by %s\n", yosys_version_str);
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}
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void write_map(std::ostream &f, bool verbose_map, bool omode)
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void write_map(std::ostream &f, bool verbose_map)
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{
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dict<int, string> input_lines;
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dict<int, string> init_lines;
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@ -952,8 +941,6 @@ struct XAigerWriter
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for (auto &it : output_lines)
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f << it.second;
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log_assert(output_lines.size() == output_bits.size());
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if (omode && output_bits.empty())
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f << "output " << output_lines.size() << " 0 __dummy_o__\n";
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latch_lines.sort();
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for (auto &it : latch_lines)
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@ -989,19 +976,12 @@ struct XAigerBackend : public Backend {
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log(" -vmap <filename>\n");
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log(" like -map, but more verbose\n");
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log("\n");
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log(" -I, -O, -B\n");
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log(" If the design contains no input/output/assert then create one\n");
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log(" dummy input/output/bad_state pin to make the tools reading the\n");
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log(" AIGER file happy.\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool ascii_mode = false;
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bool zinit_mode = false;
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bool verbose_map = false;
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bool imode = false;
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bool omode = false;
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std::string map_filename;
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log_header(design, "Executing XAIGER backend.\n");
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@ -1026,14 +1006,6 @@ struct XAigerBackend : public Backend {
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verbose_map = true;
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continue;
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}
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if (args[argidx] == "-I") {
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imode = true;
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continue;
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}
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if (args[argidx] == "-O") {
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omode = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -1043,15 +1015,15 @@ struct XAigerBackend : public Backend {
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if (top_module == nullptr)
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log_error("Can't find top module in current design!\n");
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XAigerWriter writer(top_module, zinit_mode, imode, omode);
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writer.write_aiger(*f, ascii_mode, omode);
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XAigerWriter writer(top_module, zinit_mode);
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writer.write_aiger(*f, ascii_mode);
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if (!map_filename.empty()) {
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std::ofstream mapf;
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mapf.open(map_filename.c_str(), std::ofstream::trunc);
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if (mapf.fail())
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log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
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writer.write_map(mapf, verbose_map, omode);
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writer.write_map(mapf, verbose_map);
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}
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}
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} XAigerBackend;
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@ -425,7 +425,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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handle_loops(design);
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Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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#if 0
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std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
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