mirror of https://github.com/YosysHQ/yosys.git
Cleanup write_xaiger
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b21d29598a
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@ -105,7 +105,7 @@ struct XAigerWriter
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return aig_map.at(bit);
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}
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XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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@ -624,14 +624,9 @@ struct XAigerWriter
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aig_o++;
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aig_outputs.push_back(0);
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}
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if (bmode) {
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//aig_b++;
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aig_outputs.push_back(0);
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
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void write_aiger(std::ostream &f, bool ascii_mode, bool omode)
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{
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int aig_obc = aig_o;
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int aig_obcj = aig_obc;
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@ -708,73 +703,6 @@ struct XAigerWriter
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}
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}
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if (symbols_mode)
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{
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dict<string, vector<string>> symbols;
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bool output_seen = false;
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for (auto wire : module->wires())
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{
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//if (wire->name[0] == '$')
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// continue;
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(wire); i++)
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{
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RTLIL::SigBit b(wire, i);
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if (input_bits.count(b)) {
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int a = aig_map.at(sig[i]);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
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else
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
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}
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if (output_bits.count(b)) {
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int o = ordered_outputs.at(b);
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output_seen = !miter_mode;
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if (GetSize(wire) != 1)
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
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else
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
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}
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//if (init_inputs.count(sig[i])) {
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// int a = init_inputs.at(sig[i]);
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// log_assert((a & 1) == 0);
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// if (GetSize(wire) != 1)
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// symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
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// else
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// symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
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//}
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
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if (GetSize(wire) != 1)
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symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
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else
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symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
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}
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}
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}
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if (omode && !output_seen)
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symbols["o0"].push_back("__dummy_o__");
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symbols.sort();
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for (auto &sym : symbols) {
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f << sym.first;
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std::sort(sym.second.begin(), sym.second.end());
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for (auto &s : sym.second)
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f << " " << s;
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f << std::endl;
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}
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}
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f << "c";
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if (!box_list.empty() || !ff_bits.empty()) {
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@ -931,8 +859,8 @@ struct XAigerWriter
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holes_module->design->selection_stack.pop_back();
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
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XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/, false /* omode */);
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f << "a";
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std::string buffer_str = a_buffer.str();
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@ -1055,9 +983,6 @@ struct XAigerBackend : public Backend {
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log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
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log(" uninitialized FFs.\n");
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log("\n");
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log(" -symbols\n");
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log(" include a symbol table in the generated AIGER file\n");
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log("\n");
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log(" -map <filename>\n");
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log(" write an extra file with port and latch symbols\n");
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log("\n");
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@ -1074,12 +999,9 @@ struct XAigerBackend : public Backend {
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{
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bool ascii_mode = false;
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bool zinit_mode = false;
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bool miter_mode = false;
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bool symbols_mode = false;
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bool verbose_map = false;
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bool imode = false;
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bool omode = false;
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bool bmode = false;
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std::string map_filename;
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log_header(design, "Executing XAIGER backend.\n");
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@ -1095,10 +1017,6 @@ struct XAigerBackend : public Backend {
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zinit_mode = true;
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continue;
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}
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if (args[argidx] == "-symbols") {
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symbols_mode = true;
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continue;
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}
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if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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@ -1116,10 +1034,6 @@ struct XAigerBackend : public Backend {
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omode = true;
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continue;
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}
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if (args[argidx] == "-B") {
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bmode = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -1129,8 +1043,8 @@ struct XAigerBackend : public Backend {
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if (top_module == nullptr)
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log_error("Can't find top module in current design!\n");
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XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
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writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
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XAigerWriter writer(top_module, zinit_mode, imode, omode);
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writer.write_aiger(*f, ascii_mode, omode);
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if (!map_filename.empty()) {
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std::ofstream mapf;
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