mirror of https://github.com/YosysHQ/yosys.git
Pattern matcher to check pool of bits, not exactly
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8dca8d486e
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@ -49,8 +49,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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cell->setPort("\\CLK", st.clock);
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if (st.ffA) {
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SigSpec A = cell->getPort("\\A");
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SigSpec D = st.ffA->getPort("\\D");
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cell->setPort("\\A", D.extend_u0(30, true));
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SigSpec Q = st.ffA->getPort("\\Q");
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A.replace(Q, D);
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cell->setPort("\\A", A);
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cell->setParam("\\AREG", State::S1);
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if (st.ffA->type == "$dff")
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cell->setPort("\\CEA2", State::S1);
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@ -59,8 +62,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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else log_abort();
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}
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if (st.ffB) {
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SigSpec B = cell->getPort("\\B");
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SigSpec D = st.ffB->getPort("\\D");
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cell->setPort("\\B", D.extend_u0(18, true));
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SigSpec Q = st.ffB->getPort("\\Q");
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B.replace(Q, D);
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cell->setPort("\\B", B);
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cell->setParam("\\BREG", State::S1);
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if (st.ffB->type == "$dff")
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cell->setPort("\\CEB2", State::S1);
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@ -71,7 +77,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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if (st.ffP) {
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SigSpec P = cell->getPort("\\P");
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SigSpec Q = st.ffP->getPort("\\Q");
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Q.append(P.extract(GetSize(Q), -1));
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P.replace(Q, P.extract(0, GetSize(Q)));
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cell->setPort("\\P", Q);
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cell->setParam("\\PREG", State::S1);
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if (st.ffP->type == "$dff")
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@ -11,7 +11,7 @@ match ffA
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select ffA->type.in($dff, $dffe)
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select param(ffA, \CLK_POLARITY).as_bool()
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// select nusers(port(ffA, \Q)) == 2
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index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25)
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index <SigSpec> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
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// DSP48E1 does not support clock inversion
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optional
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endmatch
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@ -25,7 +25,7 @@ match ffB
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select ffB->type.in($dff, $dffe)
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select param(ffB, \CLK_POLARITY).as_bool()
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// select nusers(port(ffB, \Q)) == 2
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index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B)
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index <SigSpec> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
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optional
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endmatch
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