mirror of https://github.com/YosysHQ/yosys.git
Improvements in "supercover" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -54,17 +54,33 @@ struct SupercoverPass : public Pass {
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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pool<SigBit> handled_bits;
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int cnt_wire = 0, cnt_bits = 0;
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log("Adding cover cells to module %s.\n", log_id(module));
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for (auto wire : module->selected_wires())
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{
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bool counted_wire = false;
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std::string src = wire->get_src_attribute();
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cnt_wire++;
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for (auto bit : SigSpec(wire))
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for (auto bit : sigmap(SigSpec(wire)))
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{
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if (bit.wire == nullptr)
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continue;
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if (handled_bits.count(bit))
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continue;
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SigSpec inv = module->Not(NEW_ID, bit);
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module->addCover(NEW_ID, bit, State::S1, src);
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module->addCover(NEW_ID, inv, State::S1, src);
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handled_bits.insert(bit);
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if (!counted_wire) {
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counted_wire = false;
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cnt_wire++;
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}
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cnt_bits++;
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}
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}
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