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Progress in memory_bram

This commit is contained in:
Clifford Wolf 2015-01-02 00:07:44 +01:00
parent 24ae156a74
commit 36c20f2ede
4 changed files with 42 additions and 23 deletions
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11
passes/memory/memory_bram.cc
View File

@ -30,6 +30,7 @@ struct rules_t
SigBit sig_clock;
SigSpec sig_addr, sig_data, sig_en;
bool effective_clkpol;
int mapped_port;
};
@ -320,6 +321,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
if (clken) {
clock_domains[pi.clocks] = clkdom;
pi.sig_clock = clkdom.first;
pi.effective_clkpol = clkdom.second;
}
pi.sig_en = sig_en;
@ -405,6 +407,7 @@ grow_read_ports:;
if (clken) {
clock_domains[pi.clocks] = clkdom;
pi.sig_clock = clkdom.first;
pi.effective_clkpol = clkdom.second;
}
pi.sig_addr = rd_addr.extract(cell_port_i*mem_abits, mem_abits);
@ -483,7 +486,13 @@ grow_read_ports:;
bram_dout.remove(i);
}
dout_cache[sig_data].first.append(addr_ok);
SigSpec addr_ok_q = addr_ok;
if (pi.clocks && !addr_ok.empty()) {
addr_ok_q = module->addWire(NEW_ID);
module->addDff(NEW_ID, pi.sig_clock, addr_ok, addr_ok_q, pi.effective_clkpol);
}
dout_cache[sig_data].first.append(addr_ok_q);
dout_cache[sig_data].second.append(bram_dout);
}

44
tests/bram/generate.py
View File

@ -13,7 +13,11 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
init = random.randrange(2)
abits = random.randrange(1, 8)
dbits = random.randrange(1, 8)
groups = random.randrange(5)
groups = random.randrange(1, 5)
# XXX
init = 0
groups = 2
if random.randrange(2):
abits = 2 ** random.randrange(1, 4)
@ -28,10 +32,12 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
clkpol = [ random.randrange(4) for i in range(groups) ]
# XXX
init = 0
ports = [ 1 for i in range(groups) ]
wrmode = [ 1 for i in range(groups) ]
transp = [ 0 for i in range(groups) ]
clocks = [ random.randrange(1, 4) for i in range(groups) ]
clocks = [ 1 for i in range(groups) ]
clkpol = [ 1 for i in range(groups) ]
wrmode[0] = 0
for p1 in range(groups):
if wrmode[p1] == 0:
@ -72,7 +78,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
tb_din = list()
tb_dout = list()
tb_addrlist = list()
tb_delay = 0
for i in range(10):
tb_addrlist.append(random.randrange(1048576))
@ -133,20 +138,22 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1])
if not always_hdr in v_always:
v_always[always_hdr] = list()
v_always[always_hdr] = [list(), list(), list()]
if wrmode[p1]:
tb_delay += 1
assign_op += " #%d" % tb_delay
for i in range(enable[p1]):
enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1])
v_always[always_hdr].append("if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange))
v_always[always_hdr][1].append("if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange))
else:
v_always[always_hdr].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf))
v_always[always_hdr][2 if transp[p1] else 0].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf))
for a in v_always:
v_stmts.append(a)
for l in v_always[a]:
for l in v_always[a][0]:
v_stmts.append(" " + l)
for l in v_always[a][1]:
v_stmts.append(" " + l)
for l in v_always[a][2]:
v_stmts.append(" " + l)
v_stmts.append("end")
@ -179,8 +186,8 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
print(" initial begin", file=tb_f)
if debug_mode:
print(" $dumpfile(\"temp/bram_%02d_%02d_tb.vcd\");" % (k1, k2), file=tb_f)
print(" $dumpvars(1, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
print(" $dumpfile(`vcd_file);", file=tb_f)
print(" $dumpvars(2, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
for p in (tb_clocks + tb_addr + tb_din):
if p[-2:] == "EN":
@ -195,14 +202,14 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
print(" #1000;", file=tb_f)
for i in range(100):
for p in tb_din:
print(" %s = %d;" % (p, random.randrange(1048576)), file=tb_f)
for p in tb_addr:
print(" %s = %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
if len(tb_clocks):
c = random.choice(tb_clocks)
print(" %s = !%s;" % (c, c), file=tb_f)
print(" #1;", file=tb_f)
for p in tb_din:
print(" %s <= %d;" % (p, random.randrange(1048576)), file=tb_f)
for p in tb_addr:
print(" %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
print(" #1000;", file=tb_f)
print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
(k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
@ -215,6 +222,9 @@ for k1 in range(5):
ref_f = file("temp/brams_%02d_ref.v" % k1, "w");
tb_f = file("temp/brams_%02d_tb.v" % k1, "w");
for f in [sim_f, ref_f, tb_f]:
print("`timescale 1 ns / 1 ns", file=f)
for k2 in range(1 if debug_mode else 10):
create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2)

2
tests/bram/run-single.sh
View File

@ -2,7 +2,7 @@
set -e
../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \
-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
iverilog -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \
iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \
temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi

8
tests/bram/run-test.sh
View File

@ -14,14 +14,14 @@ python generate.py
echo -n "all:"
for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do
for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do
echo -n " temp/job_$i$j.ok"
echo -n " temp/job_${i}_${j}.ok"
done; done
echo
for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do
for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do
echo "temp/job_$i$j.ok:"
echo " @bash run-single.sh $i $j"
echo " @echo 'Passed test $i vs $j.'"
echo "temp/job_${i}_${j}.ok:"
echo " @bash run-single.sh ${i} ${j}"
echo " @echo 'Passed test ${i}_${j}.'"
echo " @touch \$@"
done; done
} > temp/makefile