mirror of https://github.com/YosysHQ/yosys.git
Progress in bram testbench
This commit is contained in:
Clifford Wolf
parent
340e769667
commit
24ae156a74
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@ -6,11 +6,13 @@ from __future__ import print_function
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import sys
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import random
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def create_bram(dsc_f, sim_f, k1, k2):
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debug_mode = False
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def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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while True:
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init = random.randrange(2)
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abits = random.randrange(1, 16)
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dbits = random.randrange(1, 16)
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abits = random.randrange(1, 8)
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dbits = random.randrange(1, 8)
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groups = random.randrange(5)
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if random.randrange(2):
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@ -25,6 +27,12 @@ def create_bram(dsc_f, sim_f, k1, k2):
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clocks = [ random.randrange(4) for i in range(groups) ]
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clkpol = [ random.randrange(4) for i in range(groups) ]
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# XXX
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init = 0
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transp = [ 0 for i in range(groups) ]
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clocks = [ random.randrange(1, 4) for i in range(groups) ]
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clkpol = [ 1 for i in range(groups) ]
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for p1 in range(groups):
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if wrmode[p1] == 0:
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enable[p1] = 0
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@ -38,82 +46,175 @@ def create_bram(dsc_f, sim_f, k1, k2):
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if wrmode.count(0) <= ports.count(0): config_ok = False
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if config_ok: break
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print('bram bram_%03d_%03d' % (k1, k2), file=dsc_f)
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print(' init %d' % init, file=dsc_f)
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print(' abits %d' % abits, file=dsc_f)
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print(' dbits %d' % dbits, file=dsc_f)
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print(' groups %d' % groups, file=dsc_f)
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print(' ports %s' % " ".join(["%d" % i for i in ports]), file=dsc_f)
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print(' wrmode %s' % " ".join(["%d" % i for i in wrmode]), file=dsc_f)
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print(' enable %s' % " ".join(["%d" % i for i in enable]), file=dsc_f)
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print(' transp %s' % " ".join(["%d" % i for i in transp]), file=dsc_f)
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print(' clocks %s' % " ".join(["%d" % i for i in clocks]), file=dsc_f)
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print(' clkpol %s' % " ".join(["%d" % i for i in clkpol]), file=dsc_f)
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print('endbram', file=dsc_f)
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print('match bram_%03d_%03d' % (k1, k2), file=dsc_f)
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print('endmatch', file=dsc_f)
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print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f)
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print(" init %d" % init, file=dsc_f)
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print(" abits %d" % abits, file=dsc_f)
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print(" dbits %d" % dbits, file=dsc_f)
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print(" groups %d" % groups, file=dsc_f)
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print(" ports %s" % " ".join(["%d" % i for i in ports]), file=dsc_f)
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print(" wrmode %s" % " ".join(["%d" % i for i in wrmode]), file=dsc_f)
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print(" enable %s" % " ".join(["%d" % i for i in enable]), file=dsc_f)
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print(" transp %s" % " ".join(["%d" % i for i in transp]), file=dsc_f)
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print(" clocks %s" % " ".join(["%d" % i for i in clocks]), file=dsc_f)
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print(" clkpol %s" % " ".join(["%d" % i for i in clkpol]), file=dsc_f)
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print("endbram", file=dsc_f)
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print("match bram_%02d_%02d" % (k1, k2), file=dsc_f)
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print("endmatch", file=dsc_f)
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states = set()
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v_ports = set()
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v_stmts = list()
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v_always = dict()
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v_stmts.append("reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
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tb_decls = list()
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tb_clocks = list()
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tb_addr = list()
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tb_din = list()
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tb_dout = list()
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tb_addrlist = list()
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tb_delay = 0
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for i in range(10):
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tb_addrlist.append(random.randrange(1048576))
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t = random.randrange(1048576)
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for i in range(10):
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tb_addrlist.append(t ^ (1 << i))
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v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
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for p1 in range(groups):
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for p2 in range(ports[p1]):
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pf = "%c%d" % (chr(ord('A') + p1), p2 + 1)
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pf = "%c%d" % (chr(ord("A") + p1), p2 + 1)
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if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports:
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v_ports.add("CLK%d" % clocks[p1])
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v_stmts.append("input CLK%d;" % clocks[p1])
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tb_decls.append("reg CLK%d;" % clocks[p1])
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tb_clocks.append("CLK%d" % clocks[p1])
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v_ports.add("%sADDR" % pf)
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v_stmts.append("input [%d:0] %sADDR;" % (abits-1, pf))
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tb_decls.append("reg [%d:0] %sADDR;" % (abits-1, pf))
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tb_addr.append("%sADDR" % pf)
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v_ports.add("%sDATA" % pf)
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v_stmts.append("%s [%d:0] %sDATA;" % ("input" if wrmode[p1] else "output reg", dbits-1, pf))
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if wrmode[p1]:
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tb_decls.append("reg [%d:0] %sDATA;" % (dbits-1, pf))
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tb_din.append("%sDATA" % pf)
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else:
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tb_decls.append("wire [%d:0] %sDATA;" % (dbits-1, pf))
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tb_decls.append("wire [%d:0] %sDATA_R;" % (dbits-1, pf))
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tb_dout.append("%sDATA" % pf)
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if wrmode[p1] and enable[p1]:
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v_ports.add("%sEN" % pf)
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v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf))
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tb_decls.append("reg [%d:0] %sEN;" % (enable[p1]-1, pf))
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tb_din.append("%sEN" % pf)
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assign_op = "<="
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if clocks[p1] == 0:
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v_stmts.append("always @* begin")
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always_hdr = "always @* begin"
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assign_op = "="
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elif clkpol[p1] == 0:
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v_stmts.append("always @(negedge CLK%d) begin" % clocks[p1])
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always_hdr = "always @(negedge CLK%d) begin" % clocks[p1]
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elif clkpol[p1] == 1:
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v_stmts.append("always @(posedge CLK%d) begin" % clocks[p1])
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always_hdr = "always @(posedge CLK%d) begin" % clocks[p1]
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else:
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if not ('CP', clkpol[p1]) in states:
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if not ("CP", clkpol[p1]) in states:
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v_stmts.append("parameter CLKPOL%d = 0;" % clkpol[p1])
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states.add(('CP', clkpol[p1]))
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if not ('CPW', clocks[p1], clkpol[p1]) in states:
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states.add(("CP", clkpol[p1]))
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if not ("CPW", clocks[p1], clkpol[p1]) in states:
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v_stmts.append("wire CLK%d_CLKPOL%d = CLK%d == CLKPOL%d;" % (clocks[p1], clkpol[p1], clocks[p1], clkpol[p1]))
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states.add(('CPW', clocks[p1], clkpol[p1]))
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v_stmts.append("always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]))
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states.add(("CPW", clocks[p1], clkpol[p1]))
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always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1])
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if not always_hdr in v_always:
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v_always[always_hdr] = list()
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if wrmode[p1]:
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tb_delay += 1
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assign_op += " #%d" % tb_delay
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for i in range(enable[p1]):
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enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1])
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v_stmts.append(" if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange))
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v_always[always_hdr].append("if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange))
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else:
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v_stmts.append(" %sDATA %s memory[%sADDR];" % (pf, assign_op, pf))
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v_stmts.append("end")
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v_always[always_hdr].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf))
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print('module bram_%03d_%03d(%s);' % (k1, k2, ", ".join(v_ports)), file=sim_f)
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for a in v_always:
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v_stmts.append(a)
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for l in v_always[a]:
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v_stmts.append(" " + l)
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v_stmts.append("end")
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print("module bram_%02d_%02d(%s);" % (k1, k2, ", ".join(v_ports)), file=sim_f)
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for stmt in v_stmts:
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print(' %s' % stmt, file=sim_f)
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print('endmodule', file=sim_f)
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print(" %s" % stmt, file=sim_f)
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print("endmodule", file=sim_f)
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for k1 in range(10):
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dsc_f = file('temp/brams_%03d.txt' % k1, 'w');
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sim_f = file('temp/brams_%03d.v' % k1, 'w');
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print("module bram_%02d_%02d_ref(%s);" % (k1, k2, ", ".join(v_ports)), file=ref_f)
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for stmt in v_stmts:
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print(" %s" % stmt, file=ref_f)
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print("endmodule", file=ref_f)
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for k2 in range(10):
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create_bram(dsc_f, sim_f, k1, k2)
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print("module bram_%02d_%02d_tb;" % (k1, k2), file=tb_f)
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for stmt in tb_decls:
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print(" %s" % stmt, file=tb_f)
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print(" bram_%02d_%02d uut (" % (k1, k2), file=tb_f)
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print(" " + ",\n ".join([".%s(%s)" % (p, p) for p in (tb_clocks + tb_addr + tb_din + tb_dout)]), file=tb_f)
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print(" );", file=tb_f)
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print(" bram_%02d_%02d_ref ref (" % (k1, k2), file=tb_f)
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print(" " + ",\n ".join([".%s(%s)" % (p, p) for p in (tb_clocks + tb_addr + tb_din)]) + ",", file=tb_f)
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print(" " + ",\n ".join([".%s(%s_R)" % (p, p) for p in tb_dout]), file=tb_f)
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print(" );", file=tb_f)
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dsc_f.close()
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sim_f.close()
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expr_dout = "{%s}" % ", ".join(tb_dout)
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expr_dout_ref = "{%s}" % ", ".join(i + "_R" for i in tb_dout)
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print(" wire error = %s !== %s;" % (expr_dout, expr_dout_ref), file=tb_f)
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print(" initial begin", file=tb_f)
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if debug_mode:
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print(" $dumpfile(\"temp/bram_%02d_%02d_tb.vcd\");" % (k1, k2), file=tb_f)
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print(" $dumpvars(1, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
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for p in (tb_clocks + tb_addr + tb_din):
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if p[-2:] == "EN":
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print(" %s <= ~0;" % p, file=tb_f)
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else:
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print(" %s <= 0;" % p, file=tb_f)
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print(" #%d;" % (1000 + k2), file=tb_f)
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for v in [1, 0, 1, 0]:
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for p in tb_clocks:
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print(" %s = %d;" % (p, v), file=tb_f)
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print(" #1000;", file=tb_f)
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for i in range(100):
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for p in tb_din:
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print(" %s = %d;" % (p, random.randrange(1048576)), file=tb_f)
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for p in tb_addr:
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print(" %s = %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
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if len(tb_clocks):
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c = random.choice(tb_clocks)
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print(" %s = !%s;" % (c, c), file=tb_f)
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print(" #1;", file=tb_f)
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print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
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(k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
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print(" end", file=tb_f)
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print("endmodule", file=tb_f)
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for k1 in range(5):
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dsc_f = file("temp/brams_%02d.txt" % k1, "w");
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sim_f = file("temp/brams_%02d.v" % k1, "w");
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ref_f = file("temp/brams_%02d_ref.v" % k1, "w");
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tb_f = file("temp/brams_%02d_tb.v" % k1, "w");
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for k2 in range(1 if debug_mode else 10):
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create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2)
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@ -0,0 +1,9 @@
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#!/bin/bash
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set -e
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../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \
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-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
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iverilog -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \
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temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
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temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
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if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi
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exit 0
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@ -0,0 +1,32 @@
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#!/bin/bash
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# run this test many times:
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# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
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set -e
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rm -rf temp
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mkdir -p temp
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echo "generating tests.."
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python generate.py
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{
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echo -n "all:"
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for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do
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for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do
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echo -n " temp/job_$i$j.ok"
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done; done
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echo
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for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do
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for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do
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echo "temp/job_$i$j.ok:"
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echo " @bash run-single.sh $i $j"
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echo " @echo 'Passed test $i vs $j.'"
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echo " @touch \$@"
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done; done
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} > temp/makefile
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echo "running tests.."
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${MAKE:-make} -f temp/makefile
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exit 0
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