mirror of https://github.com/YosysHQ/yosys.git
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
This commit is contained in:
Eddie Hung
parent
5445cd4d00
commit
505e4c2d59
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@ -176,19 +176,30 @@ struct ShregmapTechXilinx7 : ShregmapTech
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{
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const auto &tap = *taps.begin();
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auto bit = tap.second;
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auto it = sigbit_to_shiftx_offset.find(bit);
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// If fixed-length, no fixup necessary
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if (it == sigbit_to_shiftx_offset.end())
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return true;
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auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
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newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
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newcell->setParam("\\INIT", cell->getParam("\\INIT"));
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newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL"));
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newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL"));
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newcell->setPort("\\C", cell->getPort("\\C"));
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newcell->setPort("\\D", cell->getPort("\\D"));
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newcell->setPort("\\E", cell->getPort("\\E"));
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Cell* shiftx = it->second.first;
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cell->setPort("\\L", shiftx->getPort("\\B"));
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cell->setPort("\\Q", shiftx->getPort("\\Y"));
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newcell->setPort("\\L", shiftx->getPort("\\B"));
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newcell->setPort("\\Q", shiftx->getPort("\\Y"));
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cell->module->remove(shiftx);
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return true;
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return false;
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}
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};
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@ -442,8 +453,6 @@ start_cell:
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first_cell->type = shreg_cell_type_str;
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first_cell->setPort(q_port, last_cell->getPort(q_port));
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if (!first_cell->hasPort("\\L"))
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first_cell->setPort("\\L", depth-1);
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first_cell->setParam("\\DEPTH", depth);
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if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
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@ -17,101 +17,13 @@
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*
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*/
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module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
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module \$__SHREG_ (input C, input D, input E, output Q);
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parameter DEPTH = 0;
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parameter [DEPTH-1:0] INIT = 0;
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parameter CLKPOL = 1;
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parameter ENPOL = 2;
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wire CE;
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// shregmap's INIT parameter shifts out LSB first;
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// however Xilinx expects MSB first
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function [DEPTH-1:0] brev;
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input [DEPTH-1:0] din;
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integer i;
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begin
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for (i = 0; i < DEPTH; i=i+1)
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brev[i] = din[DEPTH-1-i];
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end
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endfunction
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localparam [DEPTH-1:0] INIT_R = brev(INIT);
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parameter _TECHMAP_CONSTMSK_L_ = 0;
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parameter _TECHMAP_CONSTVAL_L_ = 0;
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generate
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if (ENPOL == 0)
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assign CE = ~E;
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else if (ENPOL == 1)
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assign CE = E;
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else
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assign CE = 1'b1;
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if (DEPTH == 1) begin
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wire _TECHMAP_FAIL_ = ~&_TECHMAP_CONSTMSK_L_ || _TECHMAP_CONSTVAL_L_ != 0;
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if (CLKPOL)
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FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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else
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FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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end else
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if (DEPTH <= 16) begin
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SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 17 && DEPTH <= 32) begin
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SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 33 && DEPTH <= 64) begin
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wire T0, T1, T2;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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\$__SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T2;
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else
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MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
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end else
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if (DEPTH > 65 && DEPTH <= 96) begin
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wire T0, T1, T2, T3, T4, T5, T6;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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\$__SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T4;
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else begin
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MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
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end
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end else
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if (DEPTH > 97 && DEPTH <= 128) begin
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wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
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\$__SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T6;
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else begin
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MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
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end
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end
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else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
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// Handle cases where depth is just 1 over a convenient value,
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if (&_TECHMAP_CONSTMSK_L_) begin
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// For constant length, use the flop
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wire T0;
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\$__SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(DEPTH-1-1), .E(E), .Q(T0));
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\$__SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(0), .E(E), .Q(Q));
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end
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else begin
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// For variable length, bump up to the next length
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\$__SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
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end
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end
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else begin
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
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end
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endgenerate
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
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endmodule
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module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
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@ -135,22 +47,77 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
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parameter _TECHMAP_CONSTMSK_L_ = 0;
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parameter _TECHMAP_CONSTVAL_L_ = 0;
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wire CE;
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generate
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if (ENPOL == 0)
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assign CE = ~E;
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else if (ENPOL == 1)
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assign CE = E;
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else
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assign CE = 1'b1;
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if (DEPTH == 1) begin
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\$__SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(0), .E(E), .Q(Q));
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end
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else if (DEPTH < 128) begin
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\$__SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
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end
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else if (DEPTH == 128) begin
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wire CE;
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if (ENPOL == 0)
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assign CE = ~E;
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else if (ENPOL == 1)
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assign CE = E;
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//wire _TECHMAP_FAIL_ = ~&_TECHMAP_CONSTMSK_L_ || _TECHMAP_CONSTVAL_L_ != 0;
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if (CLKPOL)
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FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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else
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assign CE = 1'b1;
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FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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end else
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if (DEPTH <= 16) begin
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SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 17 && DEPTH <= 32) begin
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SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 33 && DEPTH <= 64) begin
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wire T0, T1, T2;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T2;
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else
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MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
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end else
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if (DEPTH > 65 && DEPTH <= 96) begin
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wire T0, T1, T2, T3, T4, T5, T6;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T4;
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else begin
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MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
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end
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end else
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if (DEPTH > 97 && DEPTH < 128) begin
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wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T6;
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else begin
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MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
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end
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end
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else if (DEPTH < 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
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// Handle cases where depth is just 1 over a convenient value,
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if (&_TECHMAP_CONSTMSK_L_) begin
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// For constant length, use the flop
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wire T0;
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(DEPTH-1-1), .E(E), .Q(T0));
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\$__XILINX_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(0), .E(E), .Q(Q));
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end
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else begin
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// For variable length, bump up to the next length
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
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end
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end
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else if (DEPTH == 128) begin
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wire T0, T1, T2, T3, T4, T5, T6;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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