mirror of https://github.com/YosysHQ/yosys.git
Simplify and fix for MACs
This commit is contained in:
Eddie Hung
parent
4f11ff8ebd
commit
dc0c853abe
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@ -81,25 +81,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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SigSpec B = st.sigB;
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B.extend_u0(16, b_signed);
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SigSpec CD;
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bool CD_signed = false;
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if (st.muxAB != st.addAB) {
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if (st.muxA)
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CD = st.muxA->getPort("\\B");
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else if (st.muxB)
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CD = st.muxB->getPort("\\A");
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else log_abort();
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CD_signed = a_signed && b_signed; // TODO: Do muxes have [AB]_SIGNED?
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}
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else if (st.addAB) {
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if (st.addA)
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CD = st.addAB->getPort("\\B");
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else if (st.addB)
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CD = st.addAB->getPort("\\A");
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else log_abort();
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CD_signed = st.sigO_signed;
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}
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CD.extend_u0(32, CD_signed);
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SigSpec CD = st.sigCD;
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CD.extend_u0(32, st.sigCD_signed);
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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@ -161,27 +144,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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// SB_MAC16 Output Interface
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SigSpec O_lo = (st.ffO_lo ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(0,16);
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if (GetSize(O_lo) < 16)
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O_lo.append(pm.module->addWire(NEW_ID, 16-GetSize(O_lo)));
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SigSpec O_hi = (st.ffO_hi ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(16,16);
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if (GetSize(O_hi) < 16)
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O_hi.append(pm.module->addWire(NEW_ID, 16-GetSize(O_hi)));
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SigSpec O{O_hi,O_lo};
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cell->setPort("\\O", O);
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cell->setPort("\\O", st.sigO);
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bool accum = false;
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if (st.addAB) {
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if (st.addA)
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accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O);
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else if (st.addB)
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accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O);
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else log_abort();
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if (accum)
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log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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else
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log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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if (st.addA)
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accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == st.sigO);
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else if (st.addB)
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accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == st.sigO);
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else log_abort();
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if (accum)
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log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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else
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log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
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cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
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} else {
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@ -231,10 +206,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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pm.autoremove(st.mul);
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pm.autoremove(st.ffH);
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pm.autoremove(st.addAB);
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if (st.ffO_lo)
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st.ffO_lo->connections_.at("\\Q").replace(O.extract(0,16), pm.module->addWire(NEW_ID, 16));
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if (st.ffO_hi)
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st.ffO_hi->connections_.at("\\Q").replace(O.extract(16,16), pm.module->addWire(NEW_ID, 16));
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if (st.ffO_lo) {
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SigSpec O = st.sigO.extract(0,16);
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st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
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}
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if (st.ffO_hi) {
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SigSpec O = st.sigO.extract(16,16);
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st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
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}
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}
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struct Ice40DspPass : public Pass {
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@ -120,7 +120,6 @@ code addAB sigCD sigCD_signed sigO
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endcode
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match muxA
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if sigCD.empty()
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select muxA->type.in($mux)
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select nusers(port(muxA, \A)) == 2
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index <SigSpec> port(muxA, \A) === sigO
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@ -128,7 +127,6 @@ match muxA
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endmatch
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match muxB
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if sigCD.empty()
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if !muxA
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select muxB->type.in($mux)
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select nusers(port(muxB, \B)) == 2
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@ -136,20 +134,11 @@ match muxB
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optional
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endmatch
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code muxAB sigCD sigCD_signed sigO
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muxAB = addAB;
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if (muxA) {
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code muxAB
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if (muxA)
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muxAB = muxA;
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sigCD = port(muxAB, \B);
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}
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if (muxB) {
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else if (muxB)
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muxAB = muxB;
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sigCD = port(muxAB, \A);
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}
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if (muxA || muxB) {
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sigO = port(muxAB, \Y);
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sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
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}
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endcode
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match ffO_lo
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@ -166,7 +155,7 @@ match ffO_hi
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optional
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endmatch
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code clock clock_pol sigO
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code clock clock_pol sigO sigCD sigCD_signed
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if (ffO_lo || ffO_hi) {
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if (ffO_lo) {
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SigBit c = port(ffO_lo, \CLK).as_bit();
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@ -195,5 +184,19 @@ code clock clock_pol sigO
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if (port(ffO_hi, \Q) != sigO.extract(16,16))
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sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
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}
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// Loading value into output register is not
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// supported unless using accumulator
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if (muxAB && sigCD != sigO) {
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if (muxAB != addAB)
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reject;
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if (muxA)
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sigCD = port(muxAB, \B);
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else if (muxB)
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sigCD = port(muxAB, \A);
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else log_abort();
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sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
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}
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}
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endcode
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