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Automatically select new objects in abc and techmap passes

This commit is contained in:
Clifford Wolf 2013-03-08 09:16:25 +01:00
parent 79b3afa011
commit b96ffed69b
3 changed files with 19 additions and 1 deletions
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5
passes/abc/abc.cc
View File

@ -459,6 +459,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = remap_name(w->name);
module->wires[wire->name] = wire;
design->select(module, wire);
}
std::map<std::string, int> cell_stats;
@ -488,6 +489,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]);
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
@ -498,6 +500,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]);
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
if (c->type == "\\MUX") {
@ -509,6 +512,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks[0].wire->name)]);
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
assert(0);
@ -532,6 +536,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
for (auto &conn : c->connections)
cell->connections[conn.first] = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
}
}

13
passes/opt/opt_rmunused.cc
View File

@ -118,6 +118,17 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
return w2->name < w1->name;
}
static bool check_public_name(RTLIL::IdString id)
{
if (id[0] == '$')
return false;
#if 0
if (id.find(".$") == std::string::npos)
return true;
#endif
return false;
}
static void rmunused_module_signals(RTLIL::Module *module)
{
SigMap assign_map(module);
@ -157,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module)
std::vector<RTLIL::Wire*> del_wires;
for (auto &it : module->wires) {
RTLIL::Wire *wire = it.second;
if (wire->name[0] == '\\') {
if (check_public_name(wire->name)) {
RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
assign_map.apply(s2);
if (!used_signals.check_any(s2) && wire->port_id == 0) {

2
passes/techmap/techmap.cc
View File

@ -112,6 +112,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
w->port_output = false;
w->port_id = 0;
module->wires[w->name] = w;
design->select(module, w);
}
for (auto &it : tpl->cells) {
@ -122,6 +123,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
for (auto &it2 : c->connections)
apply_prefix(cell_name, it2.second, module);
module->cells[c->name] = c;
design->select(module, c);
}
for (auto &it : tpl->connections) {