mirror of https://github.com/YosysHQ/yosys.git
Made the expansion order of hierarchy deterministic
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8e9e793126
commit
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@ -261,7 +261,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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return did_something;
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}
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void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTLIL::Module *mod, int indent)
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void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> &used, RTLIL::Module *mod, int indent)
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{
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if (used.count(mod) > 0)
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return;
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@ -287,7 +287,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTL
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void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
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{
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std::set<RTLIL::Module*> used;
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std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> used;
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hierarchy_worker(design, used, top, 0);
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std::vector<RTLIL::Module*> del_modules;
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@ -523,7 +523,7 @@ struct HierarchyPass : public Pass {
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{
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did_something = false;
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std::set<RTLIL::Module*> used_modules;
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std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> used_modules;
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if (top_mod != NULL) {
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log_header(design, "Analyzing design hierarchy..\n");
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hierarchy_worker(design, used_modules, top_mod, 0);
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