Renamed extend() to extend_xx(), changed most users to extend_u0()

backends/spice/spice.cc

@@ -84,7 +84,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 				RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
 				if (cell->hasPort(wire->name)) {
 					sig = sigmap(cell->getPort(wire->name));
-					sig.extend(wire->width, false);
+					sig.extend_u0(wire->width, false);
 				}
 				port_sigs.push_back(sig);
 			}

frontends/ast/genrtlil.cc

@@ -73,7 +73,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
 {
 	if (width <= sig.size()) {
-		sig.extend(width, is_signed);
+		sig.extend_u0(width, is_signed);
 		return;
 	}
 

kernel/rtlil.cc

@@ -2590,9 +2590,9 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
 	check();
 }
 
-void RTLIL::SigSpec::extend(int width, bool is_signed)
+void RTLIL::SigSpec::extend_xx(int width, bool is_signed)
 {
-	cover("kernel.rtlil.sigspec.extend");
+	cover("kernel.rtlil.sigspec.extend_xx");
 
 	pack();
 
@@ -2600,10 +2600,9 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
 		remove(width, width_ - width);
 	
 	if (width_ < width) {
-		RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
-		if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
-				padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
-			padding = RTLIL::SigSpec(RTLIL::State::S0);
+		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
+		if (!is_signed && (padding == RTLIL::State::S1 || padding.wire))
+			padding = RTLIL::State::S0;
 		while (width_ < width)
 			append(padding);
 	}
@@ -2619,9 +2618,9 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 		remove(width, width_ - width);
 	
 	if (width_ < width) {
-		RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
+		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
 		if (!is_signed)
-			padding = RTLIL::SigSpec(RTLIL::State::S0);
+			padding = RTLIL::State::S0;
 		while (width_ < width)
 			append(padding);
 	}

kernel/rtlil.h

@@ -1057,7 +1057,7 @@ public:
 	void append(const RTLIL::SigSpec &signal);
 	void append_bit(const RTLIL::SigBit &bit);
 
-	void extend(int width, bool is_signed = false);
+	void extend_xx(int width, bool is_signed = false);
 	void extend_u0(int width, bool is_signed = false);
 
 	RTLIL::SigSpec repeat(int num) const;

passes/fsm/fsm_extract.cc

@@ -40,7 +40,7 @@ static std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> exclusive_ctrls;
 
 static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
 {
-	sig.extend(dff_out.size(), false);
+	sig.extend_u0(dff_out.size(), false);
 
 	if (sig == dff_out)
 		return true;

passes/memory/memory_collect.cc

@@ -85,12 +85,12 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			RTLIL::SigSpec data = cell->getPort("\\DATA");
 			RTLIL::SigSpec en = cell->getPort("\\EN");
 
-			clk.extend(1, false);
-			clk_enable.extend(1, false);
-			clk_polarity.extend(1, false);
-			addr.extend(addr_bits, false);
-			data.extend(memory->width, false);
-			en.extend(memory->width, false);
+			clk.extend_u0(1, false);
+			clk_enable.extend_u0(1, false);
+			clk_polarity.extend_u0(1, false);
+			addr.extend_u0(addr_bits, false);
+			data.extend_u0(memory->width, false);
+			en.extend_u0(memory->width, false);
 
 			sig_wr_clk.append(clk);
 			sig_wr_clk_enable.append(clk_enable);
@@ -112,12 +112,12 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			RTLIL::SigSpec addr = cell->getPort("\\ADDR");
 			RTLIL::SigSpec data = cell->getPort("\\DATA");
 
-			clk.extend(1, false);
-			clk_enable.extend(1, false);
-			clk_polarity.extend(1, false);
-			transparent.extend(1, false);
-			addr.extend(addr_bits, false);
-			data.extend(memory->width, false);
+			clk.extend_u0(1, false);
+			clk_enable.extend_u0(1, false);
+			clk_polarity.extend_u0(1, false);
+			transparent.extend_u0(1, false);
+			addr.extend_u0(addr_bits, false);
+			data.extend_u0(memory->width, false);
 
 			sig_rd_clk.append(clk);
 			sig_rd_clk_enable.append(clk_enable);

passes/opt/opt_const.cc

@@ -491,7 +491,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
 					cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
 					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
-					new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+					new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y);
 					goto next_cell;
 				}
@@ -504,7 +504,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if (new_a.size() == 0) {
 				cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
 				RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S1 : RTLIL::State::S0);
-				new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+				new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
 				replace_cell(assign_map, module, cell, "empty", "\\Y", new_y);
 				goto next_cell;
 			}
@@ -560,7 +560,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int());
 
 			if (GetSize(sig_a) < GetSize(sig_y))
-				sig_a.extend(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
 
 			for (int i = 0; i < GetSize(sig_y); i++) {
 				int idx = i + shift_bits;

passes/proc/proc_arst.cc

@@ -262,7 +262,7 @@ struct ProcArstPass : public Pass {
 								for (auto &chunk : act.first.chunks())
 									if (chunk.wire && chunk.wire->attributes.count("\\init")) {
 										RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
-										value.extend(chunk.wire->width, false);
+										value.extend_xx(chunk.wire->width, false);
 										arst_sig.append(chunk);
 										arst_val.append(value.extract(chunk.offset, chunk.width));
 									}

passes/sat/expose.cc

@@ -607,7 +607,7 @@ struct ExposePass : public Pass {
 							RTLIL::SigSpec sig;
 							if (cell->hasPort(p->name))
 								sig = cell->getPort(p->name);
-							sig.extend(w->width);
+							sig.extend_u0(w->width);
 							if (w->port_input)
 								module->connect(RTLIL::SigSig(sig, w));
 							else

passes/techmap/alumacc.cc

@@ -501,7 +501,7 @@ struct AlumaccWorker
 				if (GetSize(sig) > 1)
 					sig = module->ReduceOr(NEW_ID, sig);
 
-				sig.extend(GetSize(cmp_y));
+				sig.extend_u0(GetSize(cmp_y));
 				module->connect(cmp_y, sig);
 			}
 

passes/techmap/maccmap.cc

@@ -49,7 +49,7 @@ struct MaccmapWorker
 
 	void add(RTLIL::SigSpec a, bool is_signed, bool do_subtract)
 	{
-		a.extend(width, is_signed);
+		a.extend_u0(width, is_signed);
 
 		if (do_subtract) {
 			a = module->Not(NEW_ID, a);
@@ -65,10 +65,10 @@ struct MaccmapWorker
 		if (GetSize(a) < GetSize(b))
 			std::swap(a, b);
 
-		a.extend(width, is_signed);
+		a.extend_u0(width, is_signed);
 
 		if (GetSize(b) > width)
-			b.extend(width, is_signed);
+			b.extend_u0(width, is_signed);
 
 		for (int i = 0; i < GetSize(b); i++)
 			if (is_signed && i+1 == GetSize(b))

passes/techmap/simplemap.cc

@@ -32,7 +32,7 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_a = cell->getPort("\\A");
 	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-	sig_a.extend(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+	sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");