mirror of https://github.com/YosysHQ/yosys.git
Added opt_const -mux_bool
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@ -31,7 +31,7 @@ struct OptPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt [selection]\n");
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log(" opt [-mux_undef] [-mux_bool] [selection]\n");
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log("\n");
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log("This pass calls all the other opt_* passes in a useful order. This performs\n");
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log("a series of trivial optimizations and cleanups. This pass executes the other\n");
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@ -46,16 +46,30 @@ struct OptPass : public Pass {
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log(" opt_share\n");
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log(" opt_rmdff\n");
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log(" opt_clean\n");
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log(" opt_const\n");
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log(" opt_const [-mux_undef] [-mux_bool]\n");
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log(" while [changed design]\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string opt_const_args;
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log_header("Executing OPT pass (performing simple optimizations).\n");
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log_push();
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extra_args(args, 1, design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-mux_undef") {
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opt_const_args += " -mux_undef";
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continue;
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}
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if (args[argidx] == "-mux_bool") {
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opt_const_args += " -mux_bool";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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log_header("Optimizing in-memory representation of design.\n");
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design->optimize();
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@ -69,7 +83,7 @@ struct OptPass : public Pass {
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Pass::call(design, "opt_share");
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Pass::call(design, "opt_rmdff");
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Pass::call(design, "opt_clean");
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Pass::call(design, "opt_const");
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Pass::call(design, "opt_const" + opt_const_args);
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if (OPT_DID_SOMETHING == false)
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break;
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log_header("Rerunning OPT passes. (Maybe there is more to do..)\n");
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@ -42,7 +42,7 @@ void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, st
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did_something = true;
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}
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef)
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool)
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{
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if (!design->selected(module))
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return;
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@ -244,6 +244,24 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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if (mux_bool && cell->type == "$mux" && cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) {
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replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]);
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goto next_cell;
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}
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if (mux_bool && cell->type == "$mux" && cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) {
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cell->connections["\\A"] = cell->connections["\\S"];
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cell->connections.erase("\\B");
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cell->connections.erase("\\S");
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cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters.erase("\\WIDTH");
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cell->type = "$not";
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did_something = true;
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goto next_cell;
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}
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if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
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RTLIL::SigSpec new_a, new_b, new_s;
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int width = cell->connections.at("\\A").width;
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@ -392,10 +410,14 @@ struct OptConstPass : public Pass {
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log(" -mux_undef\n");
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log(" remove 'undef' inputs from $mux, $pmux and $_MUX_ cells\n");
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log("\n");
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log(" -mux_bool\n");
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log(" replace $mux cells with inverters or buffers when possible\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool mux_undef = false;
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bool mux_bool = false;
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log_header("Executing OPT_CONST pass (perform const folding).\n");
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log_push();
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@ -406,6 +428,10 @@ struct OptConstPass : public Pass {
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mux_undef = true;
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continue;
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}
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if (args[argidx] == "-mux_bool") {
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mux_bool = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -414,9 +440,9 @@ struct OptConstPass : public Pass {
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do {
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do {
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did_something = false;
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replace_const_cells(design, mod_it.second, false, mux_undef);
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replace_const_cells(design, mod_it.second, false, mux_undef, mux_bool);
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} while (did_something);
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replace_const_cells(design, mod_it.second, true, mux_undef);
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replace_const_cells(design, mod_it.second, true, mux_undef, mux_bool);
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} while (did_something);
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log_pop();
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