SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

backends/btor/btor.cc

@@ -45,9 +45,9 @@ struct BtorDumperConfig
 struct WireInfo
 {
 	RTLIL::IdString cell_name;
-	RTLIL::SigChunk *chunk;
+	const RTLIL::SigChunk *chunk;
 
-	WireInfo(RTLIL::IdString c, RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
+	WireInfo(RTLIL::IdString c, const RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
 };
 
 struct WireInfoOrder

backends/verilog/verilog_backend.cc

@@ -149,7 +149,7 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 	return true;
 }
 
-void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false)
+void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false)
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
@@ -203,7 +203,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
 	}
 }
 
-void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false)
+void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = false)
 {
 	if (chunk.wire == NULL) {
 		dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal);

frontends/ast/genrtlil.cc

@@ -311,7 +311,7 @@ struct AST_INTERNAL::ProcessGenerator
 		sig.optimize();
 		for (size_t i = 0; i < sig.chunks().size(); i++)
 		{
-			RTLIL::SigChunk &chunk = sig.chunks()[i];
+			RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
 			if (chunk.wire == NULL)
 				continue;
 

kernel/consteval.h

@@ -73,7 +73,7 @@ struct ConstEval
 		RTLIL::SigSpec current_val = values_map(sig);
 		current_val.expand();
 		for (size_t i = 0; i < current_val.chunks().size(); i++) {
-			RTLIL::SigChunk &chunk = current_val.chunks()[i];
+			const RTLIL::SigChunk &chunk = current_val.chunks()[i];
 			assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
 		}
 #endif

kernel/rtlil.cc

@@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 		RTLIL::Module *mod;
 		void operator()(RTLIL::SigSpec &sig)
 		{
-			for (auto &c : sig.chunks())
+			for (auto &c : sig.chunks_rw())
 				if (c.wire != NULL)
 					c.wire = mod->wires.at(c.wire->name);
 		}

kernel/rtlil.h

@@ -501,7 +501,7 @@ private:
 	int width_;
 
 public:
-	std::vector<RTLIL::SigChunk> &chunks() { return chunks_; }
+	std::vector<RTLIL::SigChunk> &chunks_rw() { return chunks_; }
 	const std::vector<RTLIL::SigChunk> &chunks() const { return chunks_; }
 
 	int size() const { return width_; }

kernel/sigtools.h

@@ -423,8 +423,8 @@ struct SigMap
 		assert(from.chunks().size() == to.chunks().size());
 		for (size_t i = 0; i < from.chunks().size(); i++)
 		{
-			RTLIL::SigChunk &cf = from.chunks()[i];
-			RTLIL::SigChunk &ct = to.chunks()[i];
+			const RTLIL::SigChunk &cf = from.chunks()[i];
+			const RTLIL::SigChunk &ct = to.chunks()[i];
 
 			if (cf.wire == NULL)
 				continue;
@@ -444,7 +444,7 @@ struct SigMap
 		sig.expand();
 		for (size_t i = 0; i < sig.chunks().size(); i++)
 		{
-			RTLIL::SigChunk &c = sig.chunks()[i];
+			const RTLIL::SigChunk &c = sig.chunks()[i];
 			if (c.wire != NULL) {
 				register_bit(c);
 				set_bit(c, c);
@@ -462,7 +462,7 @@ struct SigMap
 	void apply(RTLIL::SigSpec &sig) const
 	{
 		sig.expand();
-		for (auto &c : sig.chunks())
+		for (auto &c : sig.chunks_rw())
 			map_bit(c);
 		sig.optimize();
 	}

passes/cmds/delete.cc

@@ -28,7 +28,7 @@ struct DeleteWireWorker
 
 	void operator()(RTLIL::SigSpec &sig) {
 		sig.optimize();
-		for (auto &c : sig.chunks())
+		for (auto &c : sig.chunks_rw())
 			if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
 				c.wire = module->addWire(NEW_ID, c.width);
 				c.offset = 0;

passes/cmds/setundef.cc

@@ -48,7 +48,7 @@ struct SetundefWorker
 	void operator()(RTLIL::SigSpec &sig)
 	{
 		sig.expand();
-		for (auto &c : sig.chunks())
+		for (auto &c : sig.chunks_rw())
 			if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
 				c.data.bits.at(0) = next_bit();
 		sig.optimize();

passes/cmds/show.cc

@@ -179,7 +179,7 @@ struct ShowWorker
 		}
 
 		if (sig.chunks().size() == 1) {
-			RTLIL::SigChunk &c = sig.chunks()[0];
+			const RTLIL::SigChunk &c = sig.chunks()[0];
 			if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
 				if (!range_check || c.wire->width == c.width)
 						return stringf("n%d", id2num(c.wire->name));
@@ -203,7 +203,7 @@ struct ShowWorker
 			int pos = sig.size()-1;
 			int idx = single_idx_count++;
 			for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
-				RTLIL::SigChunk &c = sig.chunks()[i];
+				const RTLIL::SigChunk &c = sig.chunks()[i];
 				net = gen_signode_simple(c, false);
 				assert(!net.empty());
 				if (driver) {

passes/cmds/splitnets.cc

@@ -63,7 +63,7 @@ struct SplitnetsWorker
 	void operator()(RTLIL::SigSpec &sig)
 	{
 		sig.expand();
-		for (auto &c : sig.chunks())
+		for (auto &c : sig.chunks_rw())
 			if (splitmap.count(c.wire) > 0)
 				c = splitmap.at(c.wire).at(c.offset);
 		sig.optimize();

passes/fsm/fsm_extract.cc

@@ -92,7 +92,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
 {
 	if (dont_care.size() > 0) {
 		sig.expand();
-		for (auto &chunk : sig.chunks()) {
+		for (auto &chunk : sig.chunks_rw()) {
 			assert(chunk.width == 1);
 			if (dont_care.extract(chunk).size() > 0)
 				chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
@@ -104,7 +104,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
 	ce.values_map.apply(sig);
 
 	sig.expand();
-	for (auto &chunk : sig.chunks()) {
+	for (auto &chunk : sig.chunks_rw()) {
 		assert(chunk.width == 1);
 		if (chunk.wire != NULL)
 			chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);

passes/hierarchy/submod.cc

@@ -164,7 +164,7 @@ struct SubmodWorker
 		for (RTLIL::Cell *cell : submod.cells) {
 			RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
 			for (auto &conn : new_cell->connections)
-				for (auto &c : conn.second.chunks())
+				for (auto &c : conn.second.chunks_rw())
 					if (c.wire != NULL) {
 						assert(wire_flags.count(c.wire) > 0);
 						c.wire = wire_flags[c.wire].new_wire;

passes/memory/memory_dff.cc

@@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 
 	for (size_t i = 0; i < sig.chunks().size(); i++)
 	{
-		RTLIL::SigChunk &chunk = sig.chunks()[i];
+		RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
 
 		if (chunk.wire == NULL)
 			continue;

passes/opt/opt_const.cc

@@ -699,10 +699,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			RTLIL::SigSpec a = cell->connections["\\A"]; \
 			assign_map.apply(a); \
 			if (a.is_fully_const()) { \
-				a.optimize(); \
-				if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
 				RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
-				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
 						cell->parameters["\\A_SIGNED"].as_bool(), false, \
 						cell->parameters["\\Y_WIDTH"].as_int())); \
 				replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
@@ -715,10 +713,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			RTLIL::SigSpec b = cell->connections["\\B"]; \
 			assign_map.apply(a), assign_map.apply(b); \
 			if (a.is_fully_const() && b.is_fully_const()) { \
-				a.optimize(), b.optimize(); \
-				if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
-				if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \
-				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
 						cell->parameters["\\A_SIGNED"].as_bool(), \
 						cell->parameters["\\B_SIGNED"].as_bool(), \
 						cell->parameters["\\Y_WIDTH"].as_int())); \

passes/proc/proc_arst.cc

@@ -168,7 +168,7 @@ restart_proc_arst:
 					rspec.expand(), rval.expand();
 					for (int i = 0; i < int(rspec.chunks().size()); i++)
 						if (rspec.chunks()[i].wire == NULL)
-							rval.chunks()[i] = rspec.chunks()[i];
+							rval.chunks_rw()[i] = rspec.chunks()[i];
 					rspec.optimize(), rval.optimize();
 					RTLIL::SigSpec last_rval;
 					for (int count = 0; rval != last_rval; count++) {

passes/sat/eval.cc

@@ -73,7 +73,7 @@ struct BruteForceEquivChecker
 			sig1.expand(), sig2.expand();
 			for (size_t i = 0; i < sig1.chunks().size(); i++)
 				if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
-					sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
+					sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
 			sig1.optimize(), sig2.optimize();
 		}
 
@@ -299,7 +299,7 @@ struct VlogHammerReporter
 						log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
 					for (int i = 0; i < sig.size(); i++)
 						if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
-							sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx;
+							sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx;
 				}
 
 				log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());

passes/techmap/extract.cc

@@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
 					newCell->parameters = cell->parameters;
 					for (auto &conn : cell->connections) {
 						RTLIL::SigSpec sig = sigmap(conn.second);
-						for (auto &chunk : sig.chunks())
+						for (auto &chunk : sig.chunks_rw())
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
 						newCell->connections[conn.first] = sig;

passes/techmap/hilomap.cc

@@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo;
 void hilomap_worker(RTLIL::SigSpec &sig)
 {
 	sig.expand();
-	for (auto &c : sig.chunks()) {
+	for (auto &c : sig.chunks_rw()) {
 		if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
 			if (!singleton_mode || last_hi.width == 0) {
 				last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));

passes/techmap/techmap.cc

@@ -47,7 +47,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
 		std::string wire_name = sig.chunks()[i].wire->name;
 		apply_prefix(prefix, wire_name);
 		assert(module->wires.count(wire_name) > 0);
-		sig.chunks()[i].wire = module->wires[wire_name];
+		sig.chunks_rw()[i].wire = module->wires[wire_name];
 	}
 }