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Move lookup inside if
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@ -455,9 +455,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
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if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
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design->select(module, remap_wire);
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RTLIL::Wire *wire = module->wire(w->name);
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if (w->port_output) {
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for (int i = 0; i < GetSize(remap_wire); i++)
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RTLIL::Wire *wire = module->wire(w->name);
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for (int i = 0; i < GetSize(wire); i++)
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output_bits.insert({wire, i});
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}
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}
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