mirror of https://github.com/YosysHQ/yosys.git
Renamed hashmap.h to hashlib.h, some related improvements
This commit is contained in:
parent
3e8e483233
commit
3da46d3437
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@ -1,29 +1,23 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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#ifndef YOSYS_HASHMAP_H
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// -------------------------------------------------------
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// Written by Clifford Wolf <clifford@clifford.at> in 2014
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// -------------------------------------------------------
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#ifndef HASHLIB_H
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#include <stdexcept>
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#include <string>
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#include <vector>
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#define YOSYS_HASHTABLE_SIZE_FACTOR 3
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namespace hashlib {
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#define HASHLIB_SIZE_FACTOR 3
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// The XOR version of DJB2
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// (traditionally 5381 is used as starting value for the djb2 hash)
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@ -32,7 +26,7 @@ inline unsigned int mkhash(unsigned int a, unsigned int b) {
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}
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// The ADD version of DJB2
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// (use this version as last call for cache locality in b)
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// (use this version for cache locality in b)
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inline unsigned int mkhash_add(unsigned int a, unsigned int b) {
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return ((a << 5) + a) + b;
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}
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@ -47,10 +41,11 @@ template<typename T> struct hash_ops {
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};
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template<> struct hash_ops<int> {
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bool cmp(int a, int b) const {
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template<typename T>
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bool cmp(T a, T b) const {
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return a == b;
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}
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unsigned int hash(int a) const {
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unsigned int hash(unsigned int a) const {
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return a;
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}
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};
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@ -97,7 +92,7 @@ struct hash_obj_ops {
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}
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template<typename T>
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unsigned int hash(const T *a) const {
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return a->name.hash();
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return a->hash();
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}
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};
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@ -165,9 +160,9 @@ class dict
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entries.clear();
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counter = other.size();
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * counter);
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int new_size = hashtable_size(HASHLIB_SIZE_FACTOR * counter);
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hashtable.resize(new_size);
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new_size = new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1;
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new_size = new_size / HASHLIB_SIZE_FACTOR + 1;
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entries.reserve(new_size);
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for (auto &it : other)
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@ -243,9 +238,9 @@ class dict
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if (free_list < 0)
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{
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int i = entries.size();
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * entries.size());
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int new_size = hashtable_size(HASHLIB_SIZE_FACTOR * entries.size());
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hashtable.resize(new_size);
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entries.resize(new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1);
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entries.resize(new_size / HASHLIB_SIZE_FACTOR + 1);
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entries[i].udata = value;
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entries[i].set_next_used(0);
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counter++;
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@ -345,14 +340,14 @@ public:
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insert(*first);
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}
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iterator insert(const std::pair<K, T> &value)
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std::pair<iterator, bool> insert(const std::pair<K, T> &value)
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{
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int hash = mkhash(value.first);
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int i = lookup_index(value.first, hash);
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if (i >= 0)
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return iterator(this, i);
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return std::pair<iterator, bool>(iterator(this, i), false);
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i = insert_at(value, hash);
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return iterator(this, i);
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return std::pair<iterator, bool>(iterator(this, i), true);
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}
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void erase(const K &key)
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@ -497,9 +492,9 @@ class pool
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entries.clear();
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counter = other.size();
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * counter);
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int new_size = hashtable_size(HASHLIB_SIZE_FACTOR * counter);
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hashtable.resize(new_size);
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new_size = new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1;
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new_size = new_size / HASHLIB_SIZE_FACTOR + 1;
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entries.reserve(new_size);
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for (auto &it : other)
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@ -575,9 +570,9 @@ class pool
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if (free_list < 0)
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{
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int i = entries.size();
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int new_size = hashtable_size(YOSYS_HASHTABLE_SIZE_FACTOR * entries.size());
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int new_size = hashtable_size(HASHLIB_SIZE_FACTOR * entries.size());
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hashtable.resize(new_size);
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entries.resize(new_size / YOSYS_HASHTABLE_SIZE_FACTOR + 1);
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entries.resize(new_size / HASHLIB_SIZE_FACTOR + 1);
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entries[i].key = key;
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entries[i].set_next_used(0);
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counter++;
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@ -677,14 +672,14 @@ public:
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insert(*first);
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}
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iterator insert(const K &key)
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std::pair<iterator, bool> insert(const K &key)
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{
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int hash = mkhash(key);
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int i = lookup_index(key, hash);
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if (i >= 0)
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return iterator(this, i);
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return std::pair<iterator, bool>(iterator(this, i), false);
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i = insert_at(key, hash);
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return iterator(this, i);
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return std::pair<iterator, bool>(iterator(this, i), true);
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}
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void erase(const K &key)
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void erase(const iterator it)
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{
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int hash = mkhash(it->first);
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do_erase(it->first, hash);
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int hash = mkhash(*it);
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do_erase(*it, hash);
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}
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int count(const K &key) const
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@ -774,4 +769,6 @@ public:
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const_iterator end() const { return const_iterator(this, entries.size()); }
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};
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} /* namespace hashlib */
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#endif
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@ -270,7 +270,7 @@ struct ModWalker
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dict<RTLIL::SigBit, pool<PortBit>> signal_consumers;
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pool<RTLIL::SigBit> signal_inputs, signal_outputs;
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dict<RTLIL::Cell*, pool<RTLIL::SigBit>, hash_obj_ops> cell_outputs, cell_inputs;
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dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;
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void add_wire(RTLIL::Wire *wire)
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{
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@ -236,6 +236,9 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
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RTLIL::Design::Design()
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{
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unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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refcount_modules_ = 0;
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selection_stack.push_back(RTLIL::Selection());
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}
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@ -447,6 +450,9 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
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RTLIL::Module::Module()
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{
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unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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design = nullptr;
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refcount_wires_ = 0;
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refcount_cells_ = 0;
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struct DeleteWireWorker
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{
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RTLIL::Module *module;
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const pool<RTLIL::Wire*, hash_obj_ops> *wires_p;
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const pool<RTLIL::Wire*> *wires_p;
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void operator()(RTLIL::SigSpec &sig) {
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std::vector<RTLIL::SigChunk> chunks = sig;
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@ -1146,7 +1152,7 @@ namespace {
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};
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}
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void RTLIL::Module::remove(const pool<RTLIL::Wire*, hash_obj_ops> &wires)
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void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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{
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log_assert(refcount_wires_ == 0);
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@ -1735,6 +1741,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
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RTLIL::Wire::Wire()
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{
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unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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module = nullptr;
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width = 1;
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start_offset = 0;
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@ -1746,12 +1755,17 @@ RTLIL::Wire::Wire()
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RTLIL::Memory::Memory()
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{
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unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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width = 1;
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size = 0;
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}
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RTLIL::Cell::Cell() : module(nullptr)
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{
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unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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}
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bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
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@ -708,8 +708,14 @@ struct RTLIL::Selection
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struct RTLIL::Monitor
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{
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RTLIL::IdString name;
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Monitor() { name = stringf("$%d", autoidx++); }
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Monitor() {
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unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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}
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virtual ~Monitor() { }
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virtual void notify_module_add(RTLIL::Module*) { }
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virtual void notify_module_del(RTLIL::Module*) { }
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struct RTLIL::Design
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{
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pool<RTLIL::Monitor*, hash_obj_ops> monitors;
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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pool<RTLIL::Monitor*> monitors;
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dict<std::string, std::string> scratchpad;
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int refcount_modules_;
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struct RTLIL::Module
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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protected:
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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public:
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RTLIL::Design *design;
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pool<RTLIL::Monitor*, hash_obj_ops> monitors;
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pool<RTLIL::Monitor*> monitors;
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int refcount_wires_;
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int refcount_cells_;
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RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
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// Removing wires is expensive. If you have to remove wires, remove them all at once.
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void remove(const pool<RTLIL::Wire*, hash_obj_ops> &wires);
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void remove(const pool<RTLIL::Wire*> &wires);
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void remove(RTLIL::Cell *cell);
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void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
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@ -1031,6 +1043,9 @@ public:
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struct RTLIL::Wire
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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protected:
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// use module->addWire() and module->remove() to create or destroy wires
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friend struct RTLIL::Module;
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@ -1051,6 +1066,9 @@ public:
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struct RTLIL::Memory
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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Memory();
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RTLIL::IdString name;
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@ -1060,6 +1078,9 @@ struct RTLIL::Memory
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struct RTLIL::Cell
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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protected:
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// use module->addCell() and module->remove() to create or destroy cells
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friend struct RTLIL::Module;
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@ -124,17 +124,51 @@
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YOSYS_NAMESPACE_BEGIN
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#include "kernel/hashmap.h"
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#include "kernel/hashlib.h"
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using std::vector;
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using std::string;
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using hashlib::mkhash;
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using hashlib::mkhash_add;
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using hashlib::hash_ops;
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using hashlib::hash_cstr_ops;
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using hashlib::hash_ptr_ops;
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using hashlib::hash_obj_ops;
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using hashlib::dict;
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using hashlib::pool;
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namespace RTLIL {
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struct IdString;
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struct Const;
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struct SigBit;
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struct SigSpec;
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struct Wire;
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struct Cell;
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struct Module;
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struct Design;
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struct Monitor;
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}
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using RTLIL::IdString;
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using RTLIL::Const;
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using RTLIL::SigBit;
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using RTLIL::SigSpec;
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using RTLIL::Wire;
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using RTLIL::Cell;
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using RTLIL::Module;
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using RTLIL::Design;
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template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};
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std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
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std::string vstringf(const char *fmt, va_list ap);
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int readsome(std::istream &f, char *s, int n);
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@ -91,8 +91,8 @@ struct DeletePass : public Pass {
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continue;
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}
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pool<RTLIL::Wire*, hash_obj_ops> delete_wires;
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pool<RTLIL::Cell*, hash_obj_ops> delete_cells;
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pool<RTLIL::Wire*> delete_wires;
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pool<RTLIL::Cell*> delete_cells;
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pool<RTLIL::IdString> delete_procs;
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pool<RTLIL::IdString> delete_mems;
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|
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@ -176,7 +176,7 @@ struct SplitnetsPass : public Pass {
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module->rewrite_sigspecs(worker);
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pool<RTLIL::Wire*, hash_obj_ops> delete_wires;
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pool<RTLIL::Wire*> delete_wires;
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for (auto &it : worker.splitmap)
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delete_wires.insert(it.first);
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module->remove(delete_wires);
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|
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@ -262,7 +262,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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}
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pool<RTLIL::Wire*, hash_obj_ops> del_wires;
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pool<RTLIL::Wire*> del_wires;
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int del_wires_count = 0;
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for (auto wire : maybe_del_wires)
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|
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@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
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TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_obj_ops> cell_to_inbit;
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
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dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->cells())
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|
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@ -41,7 +41,7 @@ struct OptShareWorker
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CellTypes ct;
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int total_count;
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#ifdef USE_CELL_HASH_CACHE
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dict<const RTLIL::Cell*, std::string, hash_obj_ops> cell_hash_cache;
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dict<const RTLIL::Cell*, std::string> cell_hash_cache;
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#endif
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#ifdef USE_CELL_HASH_CACHE
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|
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@ -731,7 +731,7 @@ struct ShareWorker
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return forbidden_controls_cache.at(cell);
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pool<ModWalker::PortBit> pbits;
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pool<RTLIL::Cell*, hash_obj_ops> consumer_cells;
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pool<RTLIL::Cell*> consumer_cells;
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modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
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|
@ -803,7 +803,7 @@ struct ShareWorker
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return activation_patterns_cache.at(cell);
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const pool<RTLIL::SigBit> &cell_out_bits = modwalker.cell_outputs[cell];
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||||
pool<RTLIL::Cell*, hash_obj_ops> driven_cells, driven_data_muxes;
|
||||
pool<RTLIL::Cell*> driven_cells, driven_data_muxes;
|
||||
|
||||
for (auto &bit : cell_out_bits)
|
||||
{
|
||||
|
|
Loading…
Reference in New Issue