mirror of https://github.com/YosysHQ/yosys.git
Added "test_cell" command
This commit is contained in:
Clifford Wolf
parent
e6df25bf74
commit
273383692a
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@ -289,7 +289,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
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str += "yosys";
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if (!design->selected_active_module.empty())
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str += stringf(" [%s]", RTLIL::id2cstr(design->selected_active_module));
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if (!design->selection_stack.back().full_selection) {
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if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) {
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if (design->selected_active_module.empty())
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str += "*";
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else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 ||
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@ -1,3 +1,4 @@
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OBJS += passes/tests/test_autotb.o
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OBJS += passes/tests/test_cell.o
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@ -0,0 +1,184 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2014 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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static uint32_t xorshift32(uint32_t limit) {
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static uint32_t x = 123456789;
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x ^= x << 13;
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x ^= x >> 17;
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x ^= x << 5;
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return x % limit;
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}
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static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags)
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{
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RTLIL::Module *module = design->addModule("\\gold");
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RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
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if (cell_type_flags.find('A') != std::string::npos) {
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RTLIL::Wire *wire = module->addWire("\\A");
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wire->width = 1 + xorshift32(8);
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wire->port_input = true;
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cell->set("\\A", wire);
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}
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if (cell_type_flags.find('B') != std::string::npos) {
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RTLIL::Wire *wire = module->addWire("\\B");
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if (cell_type_flags.find('h') != std::string::npos)
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wire->width = 1 + xorshift32(6);
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else
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wire->width = 1 + xorshift32(8);
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wire->port_input = true;
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cell->set("\\B", wire);
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}
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if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
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if (cell_type_flags.find('A') != std::string::npos)
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cell->parameters["\\A_SIGNED"] = true;
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if (cell_type_flags.find('B') != std::string::npos)
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cell->parameters["\\B_SIGNED"] = true;
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}
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if (cell_type_flags.find('s') != std::string::npos) {
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if (cell_type_flags.find('A') != std::string::npos && xorshift32(2))
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cell->parameters["\\A_SIGNED"] = true;
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if (cell_type_flags.find('B') != std::string::npos && xorshift32(2))
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cell->parameters["\\B_SIGNED"] = true;
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}
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if (cell_type_flags.find('Y') != std::string::npos) {
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RTLIL::Wire *wire = module->addWire("\\Y");
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wire->width = 1 + xorshift32(8);
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wire->port_output = true;
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cell->set("\\Y", wire);
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}
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module->fixup_ports();
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cell->fixup_parameters();
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cell->check();
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}
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struct TestCellPass : public Pass {
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TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" test_cell {cell-type}\n");
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log("\n");
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log("Tests the internal implementation of the given cell type (for example '$mux')\n");
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log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell type..\n");
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log("\n");
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log("Run with '-all' instead of a cell type to run the test on all supported\n");
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log("cell types.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *current_design)
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{
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if (SIZE(args) != 2)
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log_cmd_error("Expecting exactly one argument.\n");
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std::map<std::string, std::string> cell_types;
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cell_types["$not"] = "ASY";
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cell_types["$pos"] = "ASY";
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cell_types["$bu0"] = "ASY";
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cell_types["$neg"] = "ASY";
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cell_types["$and"] = "ABSY";
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cell_types["$or"] = "ABSY";
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cell_types["$xor"] = "ABSY";
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cell_types["$xnor"] = "ABSY";
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cell_types["$reduce_and"] = "ASY";
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cell_types["$reduce_or"] = "ASY";
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cell_types["$reduce_xor"] = "ASY";
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cell_types["$reduce_xnor"] = "ASY";
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cell_types["$reduce_bool"] = "ASY";
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cell_types["$shl"] = "ABshY";
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cell_types["$shr"] = "ABshY";
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cell_types["$sshl"] = "ABshY";
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cell_types["$sshr"] = "ABshY";
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// cell_types["$shift"] = "ABshY"; <-- FIXME
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// cell_types["$shiftx"] = "ABshY";
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cell_types["$lt"] = "ABSY";
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cell_types["$le"] = "ABSY";
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cell_types["$eq"] = "ABSY";
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cell_types["$ne"] = "ABSY";
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// cell_types["$eqx"] = "ABSY";
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// cell_types["$nex"] = "ABSY";
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cell_types["$ge"] = "ABSY";
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cell_types["$gt"] = "ABSY";
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cell_types["$add"] = "ABSY";
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cell_types["$sub"] = "ABSY";
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cell_types["$mul"] = "ABSY";
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cell_types["$div"] = "ABSY";
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cell_types["$mod"] = "ABSY";
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// cell_types["$pow"] = "ABsY";
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cell_types["$logic_not"] = "ASY";
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cell_types["$logic_and"] = "ABSY";
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cell_types["$logic_or"] = "ABSY";
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// cell_types["$mux"] = "A";
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// cell_types["$pmux"] = "A";
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// cell_types["$slice"] = "A";
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// cell_types["$concat"] = "A";
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// cell_types["$safe_pmux"] = "A";
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// cell_types["$lut"] = "A";
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// cell_types["$assert"] = "A";
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if (args[1] == "-all") {
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for (auto &it : cell_types)
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Pass::call(current_design, "test_cell " + it.first);
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return;
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}
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if (cell_types.count(args[1]) == 0) {
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std::string cell_type_list;
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int charcount = 100;
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for (auto &it : cell_types) {
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if (charcount > 60) {
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cell_type_list += "\n" + it.first;
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charcount = 0;
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} else
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cell_type_list += " " + it.first;
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charcount += SIZE(it.first);
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}
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log_cmd_error("This cell type is currently not supported. Try one of these:%s\n", cell_type_list.c_str());
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}
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for (int i = 0; i < 100; i++)
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{
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RTLIL::Design *design = new RTLIL::Design;
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create_gold_module(design, args[1], cell_types.at(args[1]));
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Pass::call(design, "copy gold gate; techmap gate; opt gate; dump gold");
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Pass::call(design, "miter -equiv -flatten -ignore_gold_x gold gate miter");
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Pass::call(design, "sat -verify -enable_undef -prove trigger 0 miter");
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delete design;
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}
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}
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} TestCellPass;
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