mirror of https://github.com/YosysHQ/yosys.git
Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved
This commit is contained in:
Andrew Zonenberg
parent
f9d023c53f
commit
6da5d36968
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@ -6,6 +6,7 @@ OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_rmdff.o
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OBJS += passes/opt/opt_clean.o
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OBJS += passes/opt/opt_expr.o
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OBJS += passes/opt/opt_demorgan.o
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OBJS += passes/opt/rmports.o
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ifneq ($(SMALL),1)
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@ -0,0 +1,202 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void demorgan_worker(
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ModIndex& index,
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Cell *cell,
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unsigned int& cells_changed)
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{
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SigMap& sigmap = index.sigmap;
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auto m = cell->module;
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//TODO: Add support for reduce_xor
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//DeMorgan of XOR is either XOR (if even number of inputs) or XNOR (if odd number)
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if( (cell->type != "$reduce_and") && (cell->type != "$reduce_or") )
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return;
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auto insig = sigmap(cell->getPort("\\A"));
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log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), insig.size());
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int num_inverted = 0;
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for(int i=0; i<insig.size(); i++)
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{
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auto b = insig[i];
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//See if this bit is driven by a $not cell
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//TODO: do other stuff like nor/nand?
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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bool inverted = false;
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for(auto x : ports)
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{
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if(x.port == "\\Y" && x.cell->type == "$_NOT_")
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{
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inverted = true;
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break;
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}
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}
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if(inverted)
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num_inverted ++;
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}
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//Stop if less than half of the inputs are inverted
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if(num_inverted*2 < insig.size())
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{
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log(" %d / %d inputs are inverted, not pushing\n", num_inverted, insig.size());
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return;
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}
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//More than half of the inputs are inverted! Push through
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cells_changed ++;
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log(" %d / %d inputs are inverted, pushing inverter through reduction\n", num_inverted, insig.size());
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//For each input, either add or remove the inverter as needed
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//TODO: this duplicates the loop up above, can we refactor it?
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for(int i=0; i<insig.size(); i++)
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{
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auto b = insig[i];
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//See if this bit is driven by a $not cell
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//TODO: do other stuff like nor/nand?
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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RTLIL::Cell* srcinv = NULL;
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for(auto x : ports)
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{
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if(x.port == "\\Y" && x.cell->type == "$_NOT_")
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{
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srcinv = x.cell;
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break;
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}
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}
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//We are NOT inverted! Add an inverter
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if(!srcinv)
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{
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auto inverted_b = m->addWire(NEW_ID);
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m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
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insig[i] = inverted_b;
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}
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//We ARE inverted - bypass it
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//Don't automatically delete the inverter since other stuff might still use it
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else
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insig[i] = srcinv->getPort("\\A");
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}
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//Cosmetic fixup: If our input is just a scrambled version of one bus, rearrange it
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//Reductions are all commutative, so there's no point in having them in a weird order
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bool same_signal = true;
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RTLIL::Wire* srcwire = insig[0].wire;
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std::map<int, int> seen_bits;
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for(int i=0; i<insig.size(); i++)
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seen_bits[i] = 0;
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for(int i=0; i<insig.size(); i++)
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{
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seen_bits[insig[i].offset] ++;
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if(insig[i].wire != srcwire)
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{
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same_signal = false;
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break;
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}
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}
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if(same_signal)
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{
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//Make sure we've seen every bit exactly once
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bool every_bit_once = true;
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for(int i=0; i<insig.size(); i++)
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{
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if(seen_bits[i] != 1)
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{
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every_bit_once = false;
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break;
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}
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}
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//All good? Just use the whole wire as-is without any reordering
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//We do have to swap MSB to LSB b/c that's the way the reduction cells seem to work?
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//Unclear on why this isn't sorting properly
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//TODO: can we do SigChunks instead of single bits if we have subsets of a bus?
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if(every_bit_once && (insig.size() == srcwire->width) )
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{
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log("Rearranging bits\n");
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RTLIL::SigSpec newsig;
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for(int i=0; i<insig.size(); i++)
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newsig.append(RTLIL::SigBit(srcwire, insig.size() - i - 1));
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insig = newsig;
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insig.sort();
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}
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}
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//Push the new input signal back to the reduction (after bypassing/adding inverters)
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cell->setPort("\\A", insig);
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//Change the cell type
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if(cell->type == "$reduce_and")
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cell->type = "$reduce_or";
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else if(cell->type == "$reduce_or")
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cell->type = "$reduce_and";
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//don't change XOR
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//Add an inverter to the output
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auto inverted_output = cell->getPort("\\Y");
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auto uninverted_output = m->addWire(NEW_ID);
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m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
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cell->setPort("\\Y", uninverted_output);
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}
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struct OptDemorganPass : public Pass {
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OptDemorganPass() : Pass("opt_demorgan", "Optimize reductions with DeMorgan equivalents") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_demorgan [selection]\n");
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log("\n");
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log("This pass pushes inverters through $reduce_* cells if this will reduce the\n");
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log("overall gate count of the circuit\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> /*args*/, RTLIL::Design *design)
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{
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log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
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//int argidx = 0;
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//extra_args(args, argidx, design);
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unsigned int cells_changed = 0;
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for (auto module : design->selected_modules())
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{
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ModIndex index(module);
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for (auto cell : module->selected_cells())
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demorgan_worker(index, cell, cells_changed);
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}
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if(cells_changed)
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log("Pushed inverters through %u reductions\n", cells_changed);
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}
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} OptDemorganPass;
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PRIVATE_NAMESPACE_END
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