mirror of https://github.com/YosysHQ/yosys.git
Fixed a gcc vs. clang determinism problem in abc pass
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f674150f1c
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585fcace10
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@ -123,12 +123,15 @@ static void extract_cell(RTLIL::Cell *cell)
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assign_map.apply(sig_b);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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if (cell->type == "$_AND_")
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map_signal(sig_y, 'a', map_signal(sig_a), map_signal(sig_b));
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map_signal(sig_y, 'a', mapped_a, mapped_b);
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else if (cell->type == "$_OR_")
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map_signal(sig_y, 'o', map_signal(sig_a), map_signal(sig_b));
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map_signal(sig_y, 'o', mapped_a, mapped_b);
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else if (cell->type == "$_XOR_")
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map_signal(sig_y, 'x', map_signal(sig_a), map_signal(sig_b));
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map_signal(sig_y, 'x', mapped_a, mapped_b);
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else
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abort();
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@ -149,7 +152,11 @@ static void extract_cell(RTLIL::Cell *cell)
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assign_map.apply(sig_s);
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assign_map.apply(sig_y);
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map_signal(sig_y, 'm', map_signal(sig_a), map_signal(sig_b), map_signal(sig_s));
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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int mapped_s = map_signal(sig_s);
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map_signal(sig_y, 'm', mapped_a, mapped_b, mapped_s);
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module->cells.erase(cell->name);
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delete cell;
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