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Address requested changes - don't require non-$ name. 

Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
This commit is contained in:
Jim Lawson 2019-02-22 16:06:10 -08:00
parent 5c4a72c43e
commit 71bcc4c644
3 changed files with 14 additions and 11 deletions
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14
passes/hierarchy/hierarchy.cc
View File

@ -525,14 +525,14 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
celltype = basic_cell_type(celltype);
}
// Is this cell a module instance?
if (celltype[0] != '$') {
auto instModule = design->module(celltype);
// If there is no instance for this, issue a warning.
if (instModule == NULL) {
auto instModule = design->module(celltype);
// If there is no instance for this, issue a warning.
if (instModule == NULL) {
// but only if we're sure it is a reference to a module.
if (celltype[0] != '$')
log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
} else {
score = max(score, find_top_mod_score(design, instModule, db) + 1);
}
} else {
score = max(score, find_top_mod_score(design, instModule, db) + 1);
}
}
db[module] = score;

9
tests/various/hierarchy.sh
View File

@ -3,7 +3,8 @@
set -e
../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
echo -n " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
input a;
@ -21,7 +22,8 @@ set -e
hierarchy -auto-top
EOY
../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
echo -n " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
input a;
@ -39,7 +41,8 @@ EOY
hierarchy -auto-top
EOY
../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
echo -n " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);
input a;

2
tests/various/run-test.sh
View File

@ -9,6 +9,6 @@ shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
if [ "$shell_tests" ]; then
for s in $shell_tests; do
echo "Running $s.."
bash $s >& ${s%.sh}.log
bash $s
done
fi