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Fixed bug in freduce command

This commit is contained in:
Clifford Wolf 2014-03-07 18:44:23 +01:00
parent 6f8865d81a
commit e3b11ea2d6
1 changed files with 30 additions and 0 deletions
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30
passes/sat/freduce.cc
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@ -560,6 +560,31 @@ struct FreduceWorker
{
}
bool find_bit_in_cone(std::set<RTLIL::Cell*> &celldone, RTLIL::SigBit needle, RTLIL::SigBit haystack)
{
if (needle == haystack)
return true;
if (haystack.wire == NULL || needle.wire == NULL || drivers.count(haystack) == 0)
return false;
std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(haystack);
if (celldone.count(drv.first))
return false;
celldone.insert(drv.first);
for (auto &bit : drv.second)
if (find_bit_in_cone(celldone, needle, bit))
return true;
return false;
}
bool find_bit_in_cone(RTLIL::SigBit needle, RTLIL::SigBit haystack)
{
std::set<RTLIL::Cell*> celldone;
return find_bit_in_cone(celldone, needle, haystack);
}
void dump()
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter);
@ -674,6 +699,11 @@ struct FreduceWorker
continue;
}
if (find_bit_in_cone(grp[i].bit, grp.front().bit)) {
log(" Skipping dependency of master: %s\n", log_signal(grp[i].bit));
continue;
}
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;