mirror of https://github.com/YosysHQ/yosys.git
Added SAT-based write-port sharing to memory_share
This commit is contained in:
Clifford Wolf
parent
35edac0b31
commit
297a0962ea
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@ -18,7 +18,9 @@
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*/
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#include "kernel/rtlil.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include "kernel/modwalker.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <algorithm>
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@ -37,6 +39,8 @@ struct MemoryShareWorker
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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CellTypes cone_ct;
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std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
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std::map<std::set<std::map<RTLIL::SigBit, bool>>, RTLIL::SigBit> conditions_logic_cache;
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@ -470,6 +474,167 @@ struct MemoryShareWorker
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}
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// --------------------------------------------------------
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// Consolidate write ports using sat-based resource sharing
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// --------------------------------------------------------
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void consolidate_wr_using_sat(std::string memid, std::vector<RTLIL::Cell*> &wr_ports)
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{
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if (wr_ports.size() <= 1)
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return;
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ezDefaultSAT ez;
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SatGen satgen(&ez, &modwalker.sigmap);
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// find list of considered ports and port pairs
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std::set<int> considered_ports;
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std::set<int> considered_port_pairs;
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for (int i = 0; i < int(wr_ports.size()); i++) {
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std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
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for (auto bit : bits)
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if (bit == RTLIL::State::S1)
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goto port_is_always_active;
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if (modwalker.has_drivers(bits))
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considered_ports.insert(i);
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port_is_always_active:;
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}
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log("Consolidating write ports of memory %s using sat-based resource sharing:\n", log_id(memid));
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bool cache_clk_enable = false;
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bool cache_clk_polarity = false;
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RTLIL::SigSpec cache_clk;
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for (int i = 0; i < int(wr_ports.size()); i++)
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{
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RTLIL::Cell *cell = wr_ports.at(i);
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if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
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(cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk ||
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cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
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{
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cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
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cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
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cache_clk = sigmap(cell->connections.at("\\CLK"));
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}
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else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
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considered_port_pairs.insert(i);
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if (cache_clk_enable)
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log(" Port %d (%s) on %s %s: %s\n", i, log_id(cell),
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cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk),
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considered_ports.count(i) ? "considered" : "not considered");
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else
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log(" Port %d (%s) unclocked: %s\n", i, log_id(cell),
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considered_ports.count(i) ? "considered" : "not considered");
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}
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if (considered_port_pairs.size() < 1) {
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log(" No two subsequent ports in same clock domain considered -> nothing to consolidate.\n");
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return;
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}
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// create SAT representation of common input cone of all considered EN signals
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std::set<RTLIL::Cell*> sat_cells;
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std::set<RTLIL::SigBit> bits_queue;
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std::map<int, int> port_to_sat_variable;
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for (int i = 0; i < int(wr_ports.size()); i++)
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if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
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{
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RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
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port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
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std::vector<RTLIL::SigBit> bits = sig;
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bits_queue.insert(bits.begin(), bits.end());
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}
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while (!bits_queue.empty())
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{
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std::set<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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bits_queue.clear();
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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std::set<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
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sat_cells.insert(pbit.cell);
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}
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}
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log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
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for (auto cell : sat_cells)
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satgen.importCell(cell);
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez.numCnfVariables(), ez.numCnfClauses());
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// merge subsequent ports if possible
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for (int i = 0; i < int(wr_ports.size()); i++)
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{
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if (!considered_port_pairs.count(i))
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continue;
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if (ez.solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) {
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log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i);
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continue;
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}
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log(" Merging port %d into port %d.\n", i-1, i);
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port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
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RTLIL::SigSpec last_addr = wr_ports[i-1]->connections.at("\\ADDR");
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RTLIL::SigSpec last_data = wr_ports[i-1]->connections.at("\\DATA");
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std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->connections.at("\\EN"));
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RTLIL::SigSpec this_addr = wr_ports[i]->connections.at("\\ADDR");
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RTLIL::SigSpec this_data = wr_ports[i]->connections.at("\\DATA");
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std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
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RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
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wr_ports[i]->connections.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
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wr_ports[i]->connections.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active);
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
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RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
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RTLIL::Wire *grouped_en = module->new_wire(0, NEW_ID);
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for (int j = 0; j < int(this_en.size()); j++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
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if (!groups_en.count(key)) {
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grouped_last_en.append_bit(last_en[j]);
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grouped_this_en.append_bit(this_en[j]);
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groups_en[key] = grouped_en->width;
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grouped_en->width++;
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}
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en.append(RTLIL::SigSpec(grouped_en, 1, groups_en[key]));
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}
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module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
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wr_ports[i]->connections.at("\\EN") = en;
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module->cells.erase(wr_ports[i-1]->name);
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delete wr_ports[i-1];
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wr_ports[i-1] = NULL;
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}
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// Clean up `wr_ports': remove all NULL entries
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std::vector<RTLIL::Cell*> wr_ports_with_nulls;
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wr_ports_with_nulls.swap(wr_ports);
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for (auto cell : wr_ports_with_nulls)
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if (cell != NULL)
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wr_ports.push_back(cell);
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}
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// -------------
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// Setup and run
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// -------------
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@ -515,6 +680,21 @@ struct MemoryShareWorker
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translate_rd_feedback_to_en(it.first, it.second.first, it.second.second);
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consolidate_wr_by_addr(it.first, it.second.second);
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}
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cone_ct.setup_internals();
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cone_ct.cell_types.erase("$mul");
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cone_ct.cell_types.erase("$mod");
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cone_ct.cell_types.erase("$div");
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cone_ct.cell_types.erase("$pow");
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cone_ct.cell_types.erase("$shl");
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cone_ct.cell_types.erase("$shr");
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cone_ct.cell_types.erase("$sshl");
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cone_ct.cell_types.erase("$sshr");
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modwalker.setup(design, module, &cone_ct);
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for (auto &it : memindex)
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consolidate_wr_using_sat(it.first, it.second.second);
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}
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};
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@ -0,0 +1,25 @@
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// expect-wr-ports 1
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// expect-rd-ports 1
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module test(
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input clk,
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input wr_en1, wr_en2, wr_en3,
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input [3:0] wr_addr1, wr_addr2, wr_addr3,
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input [15:0] wr_data,
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input [3:0] rd_addr,
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output reg [31:0] rd_data
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);
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reg [31:0] mem [0:15];
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always @(posedge clk) begin
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if (wr_en1)
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mem[wr_addr1][15:0] <= wr_data;
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else if (wr_en2)
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mem[wr_addr2][23:8] <= wr_data;
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else if (wr_en3)
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mem[wr_addr3][31:16] <= wr_data;
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rd_data <= mem[rd_addr];
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end
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endmodule
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