mirror of https://github.com/YosysHQ/yosys.git
Added $dffe cell type
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@ -752,6 +752,17 @@ namespace {
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return;
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}
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if (cell->type == "$dffe") {
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param_bool("\\CLK_POLARITY");
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param_bool("\\EN_POLARITY");
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port("\\CLK", 1);
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port("\\EN", 1);
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port("\\D", param("\\WIDTH"));
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port("\\Q", param("\\WIDTH"));
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check_expected();
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return;
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}
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if (cell->type == "$dffsr") {
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param_bool("\\CLK_POLARITY");
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param_bool("\\SET_POLARITY");
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@ -302,6 +302,28 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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}
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static void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
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RTLIL::SigSpec sig_en = cell->getPort("\\EN");
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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std::string gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->setPort("\\C", sig_clk);
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gate->setPort("\\E", sig_en);
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gate->setPort("\\D", sig_d[i]);
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gate->setPort("\\Q", sig_q[i]);
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}
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}
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static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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@ -399,6 +421,7 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
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mappers["$concat"] = simplemap_concat;
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mappers["$sr"] = simplemap_sr;
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mappers["$dff"] = simplemap_dff;
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mappers["$dffe"] = simplemap_dffe;
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mappers["$dffsr"] = simplemap_dffsr;
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mappers["$adff"] = simplemap_adff;
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mappers["$dlatch"] = simplemap_dlatch;
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@ -1216,6 +1216,25 @@ end
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endmodule
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// --------------------------------------------------------
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module \$dffe (CLK, EN, D, Q);
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parameter WIDTH = 0;
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parameter CLK_POLARITY = 1'b1;
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parameter EN_POLARITY = 1'b1;
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input CLK, EN;
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input [WIDTH-1:0] D;
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output reg [WIDTH-1:0] Q;
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wire pos_clk = CLK == CLK_POLARITY;
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always @(posedge pos_clk) begin
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if (EN == EN_POLARITY) Q <= D;
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end
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endmodule
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// --------------------------------------------------------
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`ifndef SIMLIB_NOSR
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@ -59,7 +59,7 @@ module _90_simplemap_various;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
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(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
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module _90_simplemap_registers;
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endmodule
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