mirror of https://github.com/YosysHQ/yosys.git
Towards more generic "adder" function extractor
This commit is contained in:
Clifford Wolf
parent
51cbec7f75
commit
15cdda7c4b
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@ -32,6 +32,20 @@ struct AddersConfig
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bool enable_hs = false;
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};
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// http://svn.clifford.at/handicraft/2016/bindec/bindec.c
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int bindec(unsigned char v)
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{
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int r = v & 1;
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r += (~((v & 2) - 1)) & 10;
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r += (~((v & 4) - 1)) & 100;
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r += (~((v & 8) - 1)) & 1000;
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r += (~((v & 16) - 1)) & 10000;
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r += (~((v & 32) - 1)) & 100000;
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r += (~((v & 64) - 1)) & 1000000;
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r += (~((v & 128) - 1)) & 10000000;
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return r;
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}
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struct AddersWorker
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{
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const AddersConfig &config;
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@ -42,13 +56,11 @@ struct AddersWorker
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dict<SigBit, Cell*> driver;
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pool<SigBit> handled_bits;
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dict<tuple<SigBit, SigBit>, pool<SigBit>> part_xor;
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dict<tuple<SigBit, SigBit>, pool<SigBit>> part_and;
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dict<tuple<SigBit, SigBit>, pool<SigBit>> part_andnot;
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pool<tuple<SigBit, SigBit>> xorxnor2;
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pool<tuple<SigBit, SigBit, SigBit>> xorxnor3;
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dict<tuple<SigBit, SigBit, SigBit>, pool<SigBit>> part_xor3;
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dict<tuple<SigBit, SigBit, SigBit>, pool<SigBit>> part_maj;
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dict<tuple<SigBit, SigBit, SigBit>, pool<SigBit>> part_majnot;
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dict<tuple<SigBit, SigBit>, dict<int, pool<SigBit>>> func2;
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dict<tuple<SigBit, SigBit, SigBit>, dict<int, pool<SigBit>>> func3;
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AddersWorker(const AddersConfig &config, Module *module) :
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config(config), module(module), ce(module), sigmap(ce.assign_map)
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@ -75,19 +87,11 @@ struct AddersWorker
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SigBit A = SigSpec(leaves)[0];
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SigBit B = SigSpec(leaves)[1];
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bool is_xor = true;
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bool is_and = true;
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bool is_andnot_a = true;
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bool is_andnot_b = true;
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int func = 0;
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for (int i = 0; i < 4; i++)
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{
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bool a_value = (i & 1) != 0;
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bool b_value = (i & 2) != 0;
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bool xor_value = a_value != b_value;
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bool and_value = a_value && b_value;
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bool andnot_a_value = !a_value && b_value;
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bool andnot_b_value = a_value && !b_value;
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ce.push();
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ce.set(A, a_value ? State::S1 : State::S0);
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@ -98,32 +102,18 @@ struct AddersWorker
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if (!ce.eval(sig))
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log_abort();
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if (sig != xor_value)
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is_xor = false;
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if (sig != and_value)
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is_and = false;
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if (sig != andnot_a_value)
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is_andnot_a = false;
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if (sig != andnot_b_value)
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is_andnot_b = false;
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if (sig == State::S1)
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func |= 1 << i;
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ce.pop();
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}
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if (is_xor)
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part_xor[tuple<SigBit, SigBit>(A, B)].insert(root);
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// log("%04d %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(root));
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if (is_and)
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part_and[tuple<SigBit, SigBit>(A, B)].insert(root);
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if (func == 0x6 || func == 0x9)
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xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
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if (is_andnot_a)
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part_andnot[tuple<SigBit, SigBit>(B, A)].insert(root);
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if (is_andnot_b)
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part_andnot[tuple<SigBit, SigBit>(A, B)].insert(root);
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func2[tuple<SigBit, SigBit>(A, B)][func].insert(root);
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}
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if (GetSize(leaves) == 3)
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@ -134,24 +124,13 @@ struct AddersWorker
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SigBit B = SigSpec(leaves)[1];
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SigBit C = SigSpec(leaves)[2];
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bool is_xor3 = true;
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bool is_maj = true;
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bool is_maj_nota = true;
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bool is_maj_notb = true;
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bool is_maj_notc = true;
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int func = 0;
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for (int i = 0; i < 8; i++)
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{
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bool a_value = (i & 1) != 0;
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bool b_value = (i & 2) != 0;
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bool c_value = (i & 4) != 0;
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bool xor3_value = (a_value != b_value) != c_value;
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bool maj_value = (a_value && b_value) || (a_value && c_value) || (b_value && c_value);
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bool maj_nota_value = (!a_value && b_value) || (!a_value && c_value) || (b_value && c_value);
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bool maj_notb_value = (a_value && !b_value) || (a_value && c_value) || (!b_value && c_value);
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bool maj_notc_value = (a_value && b_value) || (a_value && !c_value) || (b_value && !c_value);
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ce.push();
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ce.set(A, a_value ? State::S1 : State::S0);
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ce.set(B, b_value ? State::S1 : State::S0);
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@ -162,38 +141,18 @@ struct AddersWorker
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if (!ce.eval(sig))
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log_abort();
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if (sig != xor3_value)
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is_xor3 = false;
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if (sig != maj_value)
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is_maj = false;
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if (sig != maj_nota_value)
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is_maj_nota = false;
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if (sig != maj_notb_value)
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is_maj_notb = false;
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if (sig != maj_notc_value)
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is_maj_notc = false;
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if (sig == State::S1)
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func |= 1 << i;
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ce.pop();
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}
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if (is_xor3)
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part_xor3[tuple<SigBit, SigBit, SigBit>(A, B, C)].insert(root);
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// log("%08d %s %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(C), log_signal(root));
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if (is_maj)
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part_maj[tuple<SigBit, SigBit, SigBit>(A, B, C)].insert(root);
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if (func == 0x69 || func == 0x96)
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xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
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if (is_maj_nota)
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part_majnot[tuple<SigBit, SigBit, SigBit>(B, C, A)].insert(root);
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if (is_maj_notb)
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part_majnot[tuple<SigBit, SigBit, SigBit>(A, C, B)].insert(root);
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if (is_maj_notc)
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part_majnot[tuple<SigBit, SigBit, SigBit>(A, B, C)].insert(root);
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func3[tuple<SigBit, SigBit, SigBit>(A, B, C)][func].insert(root);
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}
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}
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@ -229,118 +188,6 @@ struct AddersWorker
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}
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}
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void make_fa(SigBit A, SigBit B, SigBit C, const pool<SigBit> &sum_out, const pool<SigBit> &carry_out)
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{
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if (!config.enable_fa)
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return;
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Wire *so = module->addWire(NEW_ID);
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Wire *co = module->addWire(NEW_ID);
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Cell *cell = module->addCell(NEW_ID, "$__fa");
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\C", C);
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cell->setPort("\\SO", so);
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cell->setPort("\\CO", co);
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log("New full adder %s in module %s: A=%s B=%s C=%s\n", log_id(cell), log_id(module), log_signal(A), log_signal(B), log_signal(C));
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for (auto bit : sum_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, so);
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handled_bits.insert(bit);
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log(" sum out: %s\n", log_signal(bit));
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}
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for (auto bit : carry_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, co);
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handled_bits.insert(bit);
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log(" carry out: %s\n", log_signal(bit));
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}
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}
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void make_ha(SigBit A, SigBit B, const pool<SigBit> &sum_out, const pool<SigBit> &carry_out)
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{
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if (!config.enable_ha)
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return;
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Wire *so = module->addWire(NEW_ID);
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Wire *co = module->addWire(NEW_ID);
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Cell *cell = module->addCell(NEW_ID, "$__ha");
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\SO", so);
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cell->setPort("\\CO", co);
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log("New half adder %s in module %s: A=%s B=%s\n", log_id(cell), log_id(module), log_signal(A), log_signal(B));
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for (auto bit : sum_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, so);
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handled_bits.insert(bit);
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log(" sum out: %s\n", log_signal(bit));
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}
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for (auto bit : carry_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, co);
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handled_bits.insert(bit);
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log(" carry out: %s\n", log_signal(bit));
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}
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}
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void make_hs(SigBit A, SigBit B, const pool<SigBit> &sum_out, const pool<SigBit> &carry_out)
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{
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if (!config.enable_hs)
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return;
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Wire *so = module->addWire(NEW_ID);
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Wire *co = module->addWire(NEW_ID);
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Cell *cell = module->addCell(NEW_ID, "$__hs");
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\SO", so);
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cell->setPort("\\CO", co);
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log("New half subtractor %s in module %s: A=%s B=%s\n", log_id(cell), log_id(module), log_signal(A), log_signal(B));
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for (auto bit : sum_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, so);
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handled_bits.insert(bit);
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log(" sum out: %s\n", log_signal(bit));
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}
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for (auto bit : carry_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, co);
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handled_bits.insert(bit);
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log(" carry out: %s\n", log_signal(bit));
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}
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}
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void run()
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{
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for (auto it : driver)
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@ -352,31 +199,35 @@ struct AddersWorker
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find_partitions(root, leaves, cache, 5, 10);
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}
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for (auto &it : part_xor3)
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for (auto &key : xorxnor3)
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{
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SigBit A = get<0>(it.first);
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SigBit B = get<1>(it.first);
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SigBit C = get<2>(it.first);
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SigBit A = get<0>(key);
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SigBit B = get<1>(key);
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SigBit C = get<2>(key);
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// FIXME: Add support for full subtractors
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log("3-Input XOR/XNOR %s %s %s:\n", log_signal(A), log_signal(B), log_signal(C));
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if (part_maj.count(tuple<SigBit, SigBit, SigBit>(A, B, C)))
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make_fa(A, B, C, it.second, part_maj.at(tuple<SigBit, SigBit, SigBit>(A, B, C)));
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for (auto &it : func3.at(key)) {
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log(" %08d ->", bindec(it.first));
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for (auto bit : it.second)
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log(" %s", log_signal(bit));
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log("\n");
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}
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}
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for (auto &it : part_xor)
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for (auto &key : xorxnor2)
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{
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SigBit A = get<0>(it.first);
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SigBit B = get<1>(it.first);
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SigBit A = get<0>(key);
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SigBit B = get<1>(key);
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if (part_andnot.count(tuple<SigBit, SigBit>(A, B)))
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make_hs(A, B, it.second, part_andnot.at(tuple<SigBit, SigBit>(A, B)));
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log("2-Input XOR/XNOR %s %s:\n", log_signal(A), log_signal(B));
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if (part_andnot.count(tuple<SigBit, SigBit>(B, A)))
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make_hs(B, A, it.second, part_andnot.at(tuple<SigBit, SigBit>(B, A)));
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if (part_and.count(tuple<SigBit, SigBit>(A, B)))
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make_ha(A, B, it.second, part_and.at(tuple<SigBit, SigBit>(A, B)));
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for (auto &it : func2.at(key)) {
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log(" %04d ->", bindec(it.first));
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for (auto bit : it.second)
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log(" %s", log_signal(bit));
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log("\n");
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}
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}
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}
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};
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