riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added "techmap -map %{design-name}"

This commit is contained in:
Clifford Wolf 2014-07-29 16:06:27 +02:00
parent 397b00252d
commit 03c96f9ce7
4 changed files with 29 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
kernel/rtlil.cc
View File

@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
}
}
RTLIL::Design::Design()
{
refcount_modules_ = 0;
}
RTLIL::Design::~Design()
{
for (auto it = modules_.begin(); it != modules_.end(); it++)

5
kernel/rtlil.h
View File

@ -352,11 +352,16 @@ struct RTLIL::Design
std::map<RTLIL::IdString, RTLIL::Selection> selection_vars;
std::string selected_active_module;
Design();
~Design();
RTLIL::ObjRange<RTLIL::Module*> modules();
RTLIL::Module *module(RTLIL::IdString name);
bool has(RTLIL::IdString id) const {
return modules_.count(id) != 0;
}
void add(RTLIL::Module *module);
RTLIL::Module *addModule(RTLIL::IdString name);
void remove(RTLIL::Module *module);

6
passes/techmap/extract.cc
View File

@ -603,9 +603,9 @@ struct ExtractPass : public Pass {
delete map;
log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
}
for (auto &it : saved_designs.at(filename.substr(1))->modules_)
if (!map->modules_.count(it.first))
map->modules_[it.first] = it.second->clone();
for (auto mod : saved_designs.at(filename.substr(1))->modules())
if (!map->has(mod->name))
map->add(mod->clone());
}
else
{

23
passes/techmap/techmap.cc
View File

@ -656,13 +656,22 @@ struct TechmapPass : public Pass {
Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
fclose(f);
} else
for (auto &fn : map_files) {
FILE *f = fopen(fn.c_str(), "rt");
if (f == NULL)
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
fclose(f);
}
for (auto &fn : map_files)
if (fn.substr(0, 1) == "%") {
if (!saved_designs.count(fn.substr(1))) {
delete map;
log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
}
for (auto mod : saved_designs.at(fn.substr(1))->modules())
if (!map->has(mod->name))
map->add(mod->clone());
} else {
FILE *f = fopen(fn.c_str(), "rt");
if (f == NULL)
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
fclose(f);
}
std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
for (auto &it : map->modules_) {