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write_verilog with *.v extension

This commit is contained in:
Eddie Hung 2019-07-10 20:25:59 -07:00
parent ea6ffea2cd
commit 9f608d6be3
1 changed files with 1 additions and 1 deletions
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2
passes/techmap/abc9.cc
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@ -435,7 +435,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// count_gates, GetSize(signal_list), count_input, count_output);
#if 0
Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str()));
Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str()));
#endif
Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));