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Fix clk_pol for FD*_1

This commit is contained in:
Eddie Hung 2019-07-10 20:10:20 -07:00
parent 7899a06ed6
commit ea6ffea2cd
2 changed files with 3 additions and 4 deletions
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1
backends/aiger/xaiger.cc
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@ -311,7 +311,6 @@ struct XAigerWriter
alias_map[O] = q;
undriven_bits.erase(O);
ff_bits.emplace_back(q);
}
else {
for (const auto &conn : cell->connections()) {

6
techlibs/xilinx/abc_ff.v
View File

@ -157,7 +157,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *) output Q,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter \$abc_flop_clk_pol = 1'b1;
parameter \$abc_flop_clk_pol = 1'b0;
parameter \$abc_flop_en_pol = 1'b1;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
endmodule
@ -184,7 +184,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *) output Q,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter \$abc_flop_clk_pol = 1'b1;
parameter \$abc_flop_clk_pol = 1'b0;
parameter \$abc_flop_en_inv = 1'b1;
assign Q = (CE && !CLR) ? D : \$pastQ ;
endmodule
@ -211,7 +211,7 @@ module \$__ABC_FDPE_1 ((* abc_flop_q *) output Q,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
parameter \$abc_flop_clk_pol = 1'b0;
parameter \$abc_flop_en_pol = 1'b1;
assign Q = (CE && !PRE) ? D : \$pastQ ;
endmodule