mirror of https://github.com/YosysHQ/yosys.git
remove buffers in opt_clean
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7019bc00e4
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600c6cb013
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@ -293,6 +293,19 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
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if (verbose)
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log("Finding unused cells or wires in module %s..\n", module->name.c_str());
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std::vector<RTLIL::Cell*> delcells;
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for (auto cell : module->cells())
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if (cell->type == "$pos") {
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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RTLIL::SigSpec a = cell->getPort("\\A");
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RTLIL::SigSpec y = cell->getPort("\\Y");
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a.extend_u0(SIZE(y), is_signed);
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module->connect(y, a);
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delcells.push_back(cell);
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}
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for (auto cell : delcells)
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module->remove(cell);
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rmunused_module_cells(module, verbose);
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rmunused_module_signals(module, purge_mode, verbose);
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}
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