mirror of https://github.com/YosysHQ/yosys.git
Added "aig" pass
This commit is contained in:
Clifford Wolf
parent
9500b564ac
commit
66f9ee412a
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@ -44,12 +44,42 @@ unsigned int AigNode::hash() const
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struct AigMaker
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{
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Aig *aig;
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Cell *cell;
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idict<AigNode> aig_indices;
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AigMaker(Aig *aig) : aig(aig) { }
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int the_true_node;
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int the_false_node;
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int inport(IdString portname, int portbit, bool inverter = false)
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AigMaker(Aig *aig, Cell *cell) : aig(aig), cell(cell)
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{
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the_true_node = -1;
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the_false_node = -1;
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}
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int bool_node(bool value)
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{
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AigNode node;
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node.portbit = -1;
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node.inverter = !value;
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node.left_parent = -1;
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node.right_parent = -1;
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if (!aig_indices.count(node)) {
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aig_indices.expect(node, GetSize(aig->nodes));
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aig->nodes.push_back(node);
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}
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return aig_indices.at(node);
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}
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int inport(IdString portname, int portbit = 0, bool inverter = false)
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{
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if (portbit >= GetSize(cell->getPort(portname))) {
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if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
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return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
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return bool_node(!inverter);
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}
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AigNode node;
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node.portname = portname;
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node.portbit = portbit;
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@ -65,8 +95,16 @@ struct AigMaker
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return aig_indices.at(node);
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}
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int gate(int left_parent, int right_parent, bool inverter = false)
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int not_inport(IdString portname, int portbit = 0)
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{
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return inport(portname, portbit, true);
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}
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int and_gate(int left_parent, int right_parent, bool inverter = false)
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{
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if (left_parent > right_parent)
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std::swap(left_parent, right_parent);
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AigNode node;
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node.portbit = -1;
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node.inverter = inverter;
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@ -81,9 +119,15 @@ struct AigMaker
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return aig_indices.at(node);
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}
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void outport(int node, IdString portname, int portbit)
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int nand_gate(int left_parent, int right_parent)
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{
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aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
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return and_gate(left_parent, right_parent, true);
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}
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void outport(int node, IdString portname, int portbit = 0)
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{
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if (portbit < GetSize(cell->getPort(portname)))
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aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
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}
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};
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@ -92,28 +136,110 @@ Aig::Aig(Cell *cell)
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if (cell->type[0] != '$')
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return;
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AigMaker mk(this);
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AigMaker mk(this, cell);
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name = cell->type.str();
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cell->parameters.sort();
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for (auto p : cell->parameters)
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name += stringf(":%d", p.second.as_int());
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if (cell->type == "$_AND_" || cell->type == "$_NAND_")
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if (cell->type.in("$and", "$_AND_", "$_NAND_"))
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{
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int A = mk.inport("A", 0);
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int B = mk.inport("B", 0);
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int Y = mk.gate(A, B, cell->type == "$_NAND_");
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mk.outport(Y, "Y", 0);
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int B = mk.inport("\\B", i);
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int Y = mk.and_gate(A, B, cell->type == "$_NAND_");
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mk.outport(Y, "\\Y", i);
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}
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return;
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}
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if (cell->type == "$_OR_" || cell->type == "$_NOR_")
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if (cell->type.in("$or", "$_OR_", "$_NOR_"))
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{
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int A = mk.inport("A", 0, true);
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int B = mk.inport("B", 0, true);
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int Y = mk.gate(A, B, cell->type == "$_OR_");
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mk.outport(Y, "Y", 0);
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.not_inport("\\A", i);
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int B = mk.not_inport("\\B", i);
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int Y = mk.and_gate(A, B, cell->type != "$_NOR_");
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mk.outport(Y, "\\Y", i);
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}
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return;
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}
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if (cell->type.in("$xor", "$xnor", "$_XOR_", "$_XNOR_"))
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{
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int B = mk.inport("\\B", i);
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int NA = mk.not_inport("\\A", i);
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int NB = mk.not_inport("\\B", i);
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int NOT_AB = mk.nand_gate(A, B);
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int NOT_NAB = mk.nand_gate(NA, NB);
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int Y = mk.and_gate(NOT_AB, NOT_NAB, !cell->type.in("$xor", "$_XOR_"));
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mk.outport(Y, "\\Y", i);
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}
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return;
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}
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if (cell->type.in("$mux", "$_MUX_"))
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{
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int S = mk.inport("\\S");
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int NS = mk.not_inport("\\S");
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int B = mk.inport("\\B", i);
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int NOT_SB = mk.nand_gate(S, B);
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int NOT_NSA = mk.nand_gate(NS, A);
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int Y = mk.nand_gate(NOT_SB, NOT_NSA);
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mk.outport(Y, "\\Y", i);
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}
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return;
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}
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if (cell->type == "$_AOI3_")
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{
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int A = mk.inport("\\A");
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int B = mk.inport("\\B");
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int NC = mk.not_inport("\\C");
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int NOT_AB = mk.nand_gate(A, B);
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int Y = mk.and_gate(NOT_AB, NC);
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mk.outport(Y, "\\Y");
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return;
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}
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if (cell->type == "$_OAI3_")
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{
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int NA = mk.not_inport("\\A");
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int NB = mk.not_inport("\\B");
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int C = mk.inport("\\C");
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int NOT_NAB = mk.nand_gate(NA, NB);
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int Y = mk.nand_gate(NOT_NAB, C);
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mk.outport(Y, "\\Y");
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return;
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}
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if (cell->type == "$_AOI4_")
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{
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int A = mk.inport("\\A");
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int B = mk.inport("\\B");
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int C = mk.inport("\\C");
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int D = mk.inport("\\D");
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int NOT_AB = mk.nand_gate(A, B);
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int NOT_CD = mk.nand_gate(C, D);
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int Y = mk.and_gate(NOT_AB, NOT_CD);
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mk.outport(Y, "\\Y");
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return;
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}
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if (cell->type == "$_OAI4_")
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{
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int NA = mk.not_inport("\\A");
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int NB = mk.not_inport("\\B");
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int NC = mk.not_inport("\\C");
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int ND = mk.not_inport("\\D");
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int NOT_NAB = mk.nand_gate(NA, NB);
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int NOT_NCD = mk.nand_gate(NC, ND);
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int Y = mk.nand_gate(NOT_NAB, NOT_NCD);
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mk.outport(Y, "\\Y");
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return;
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}
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@ -18,6 +18,7 @@ OBJS += passes/techmap/dff2dffe.o
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OBJS += passes/techmap/dffinit.o
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OBJS += passes/techmap/pmuxtree.o
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OBJS += passes/techmap/muxcover.o
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OBJS += passes/techmap/aig.o
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endif
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GENFILES += passes/techmap/techmap.inc
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@ -0,0 +1,148 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/cellaigs.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AigPass : public Pass {
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AigPass() : Pass("aig", "convert logic to and-inverter circuit") { }
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virtual void help()
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{
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log("\n");
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log(" aig [options] [selection]\n");
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log("\n");
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log("Replace all logic cells with circuits made of only $_AND_ and\n");
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log("$_NOT_ cells.\n");
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log("\n");
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log(" -nand\n");
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log(" Enable creation of $_NAND_ cells\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool nand_mode = false;
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log_header("Executing AIG pass (converting logic to AIG).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-nand") {
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nand_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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vector<Cell*> replaced_cells;
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int not_replaced_count = 0;
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dict<IdString, int> stat_replaced;
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dict<IdString, int> stat_not_replaced;
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int orig_num_cells = GetSize(module->cells());
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for (auto cell : module->selected_cells())
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{
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Aig aig(cell);
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if (cell->type == "$_AND_" || cell->type == "$_NOT_")
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aig.name.clear();
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if (nand_mode && cell->type == "$_NAND_")
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aig.name.clear();
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if (aig.name.empty()) {
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not_replaced_count++;
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stat_not_replaced[cell->type]++;
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continue;
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}
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vector<SigBit> sigs;
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dict<pair<int, int>, SigBit> and_cache;
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for (int node_idx = 0; node_idx < GetSize(aig.nodes); node_idx++)
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{
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SigBit bit;
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auto &node = aig.nodes[node_idx];
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if (node.portbit >= 0) {
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bit = cell->getPort(node.portname)[node.portbit];
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} else if (node.left_parent < 0 && node.right_parent < 0) {
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bit = node.inverter ? State::S0 : State::S1;
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} else {
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SigBit A = sigs.at(node.left_parent);
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SigBit B = sigs.at(node.right_parent);
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if (nand_mode && node.inverter) {
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bit = module->NandGate(NEW_ID, A, B);
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goto nand_inverter;
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} else {
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pair<int, int> key(node.left_parent, node.right_parent);
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if (and_cache.count(key))
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bit = and_cache.at(key);
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else
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bit = module->AndGate(NEW_ID, A, B);
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}
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}
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if (node.inverter)
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bit = module->NotGate(NEW_ID, bit);
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nand_inverter:
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for (auto &op : node.outports)
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module->connect(cell->getPort(op.first)[op.second], bit);
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sigs.push_back(bit);
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}
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replaced_cells.push_back(cell);
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stat_replaced[cell->type]++;
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}
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if (not_replaced_count == 0 && replaced_cells.empty())
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continue;
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log("Module %s: replaced %d cells with %d new cells, skipped %d cells.\n", log_id(module),
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GetSize(replaced_cells), GetSize(module->cells()) - orig_num_cells, not_replaced_count);
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if (!stat_replaced.empty()) {
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stat_replaced.sort();
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log(" replaced %d cell types:\n", GetSize(stat_replaced));
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for (auto &it : stat_replaced)
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log("%8d %s\n", it.second, log_id(it.first));
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}
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if (!stat_not_replaced.empty()) {
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stat_not_replaced.sort();
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log(" not replaced %d cell types:\n", GetSize(stat_not_replaced));
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for (auto &it : stat_not_replaced)
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log("%8d %s\n", it.second, log_id(it.first));
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}
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for (auto cell : replaced_cells)
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module->remove(cell);
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}
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}
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} AigPass;
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PRIVATE_NAMESPACE_END
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