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synth_ice40 now flattens by default

This commit is contained in:
Clifford Wolf 2015-06-09 20:28:17 +02:00
parent e49e2662aa
commit 9500b564ac
1 changed files with 8 additions and 4 deletions
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12
techlibs/ice40/synth_ice40.cc
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@ -60,8 +60,8 @@ struct SynthIce40Pass : public Pass {
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -flatten\n");
log(" flatten design before synthesis\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
@ -79,7 +79,7 @@ struct SynthIce40Pass : public Pass {
log(" read_verilog -lib +/ice40/cells_sim.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
log(" flatten: (unless -noflatten)\n");
log(" proc\n");
log(" flatten\n");
log("\n");
@ -133,7 +133,7 @@ struct SynthIce40Pass : public Pass {
std::string blif_file, edif_file;
bool nocarry = false;
bool nobram = false;
bool flatten = false;
bool flatten = true;
bool retime = false;
size_t argidx;
@ -163,6 +163,10 @@ struct SynthIce40Pass : public Pass {
flatten = true;
continue;
}
if (args[argidx] == "-noflatten") {
flatten = false;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;