mirror of https://github.com/YosysHQ/yosys.git
Added "check -noinit"
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@ -31,7 +31,7 @@ struct CheckPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" check [selection]\n");
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log(" check [options] [selection]\n");
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log("\n");
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log("This pass identifies the following problems in the current design:\n");
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log("\n");
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@ -41,15 +41,27 @@ struct CheckPass : public Pass {
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log("\n");
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log(" - used wires that do not have a driver\n");
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log("\n");
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log("When called with -noinit then this command also checks for wires which have\n");
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log("the 'init' attribute set.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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int counter = 0;
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bool noinit = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-noinit") {
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noinit = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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log_header("Executing CHECK pass (checking for obvious problems).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_whole_modules_warn())
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{
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if (module->has_processes_warn())
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@ -93,6 +105,10 @@ struct CheckPass : public Pass {
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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if (bit.wire) used_wires.insert(bit);
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if (noinit && wire->attributes.count("\\init")) {
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log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
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counter++;
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}
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}
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for (auto it : wire_drivers)
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