mirror of https://github.com/YosysHQ/yosys.git
Fixed hierarchy pass for hierarchies of parametric modules
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@ -152,6 +152,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
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RTLIL::Module *mod = design->modules[cell->type];
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cell->type = mod->derive(design, cell->parameters);
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cell->parameters.clear();
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did_something = true;
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}
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if (did_something)
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