mirror of https://github.com/YosysHQ/yosys.git
Added show -color support for cells and finished show -label implementation
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af325bf206
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@ -81,7 +81,7 @@ struct ShowWorker
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if (c.wire != NULL)
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for (auto &s : color_selections)
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if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
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return stringf("color=\"%s\", fontcolor=\"%d\"", s.first.c_str(), s.first.c_str());
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return stringf("color=\"%s\"", s.first.c_str());
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}
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return defaultColor;
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}
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@ -110,6 +110,24 @@ struct ShowWorker
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return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits);
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}
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const char *findColor(std::string member_name)
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{
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for (auto &s : color_selections)
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if (s.second.selected_member(module->name, member_name)) {
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dot_escape_store.push_back(stringf(", color=\"%s\"", s.first.c_str()));
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return dot_escape_store.back().c_str();
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}
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return "";
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}
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const char *findLabel(std::string member_name)
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{
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for (auto &s : label_selections)
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if (s.second.selected_member(module->name, RTLIL::escape_id(member_name)))
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return escape(s.first);
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return escape(member_name, true);
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}
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const char *escape(std::string id, bool is_name = false)
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{
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if (id.size() == 0)
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@ -165,7 +183,7 @@ struct ShowWorker
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if (!range_check || c.wire->width == c.width)
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return stringf("n%d", id2num(c.wire->name));
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} else {
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fprintf(f, "v%d [ label=\"%s\" ];\n", single_idx_count, escape(log_signal(c), true));
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fprintf(f, "v%d [ label=\"%s\" ];\n", single_idx_count, findLabel(log_signal(c)));
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return stringf("v%d", single_idx_count++);
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}
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}
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@ -296,7 +314,7 @@ struct ShowWorker
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shape = "octagon";
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if (it.first[0] == '\\') {
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fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
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id2num(it.first), shape, escape(it.first),
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id2num(it.first), shape, findLabel(it.first),
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nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str());
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if (it.second->port_input)
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all_sources.insert(stringf("n%d", id2num(it.first)));
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@ -341,7 +359,7 @@ struct ShowWorker
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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label_string += stringf("}|%s\\n%s|{", escape(it.first, true), escape(it.second->type));
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label_string += stringf("}|%s\\n%s|{", findLabel(it.first), escape(it.second->type));
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for (auto &p : out_ports)
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label_string += stringf("<p%d> %s|", id2num(p), escape(p));
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@ -358,12 +376,12 @@ struct ShowWorker
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#ifdef CLUSTER_CELLS_AND_PORTBOXES
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if (!code.empty())
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fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\" ];\n%s}\n",
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id2num(it.first), id2num(it.first), label_string.c_str(), code.c_str());
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fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n",
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id2num(it.first), id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str());
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else
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#endif
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fprintf(f, "c%d [ shape=record, label=\"%s\" ];\n%s",
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id2num(it.first), label_string.c_str(), code.c_str());
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fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s",
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id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str());
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}
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for (auto &it : module->processes)
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@ -401,7 +419,7 @@ struct ShowWorker
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std::string proc_src = RTLIL::unescape_id(proc->name);
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if (proc->attributes.count("\\src") > 0)
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proc_src = proc->attributes.at("\\src").decode_string();
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fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, escape(proc->name, true), proc_src.c_str());
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fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
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}
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for (auto &conn : module->connections)
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@ -457,7 +475,7 @@ struct ShowWorker
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continue;
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}
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if (it.second.in.size() == 0 || it.second.out.size() == 0)
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fprintf(f, "%s [ shape=diamond, label=\"%s\" ];\n", it.first.c_str(), escape(wires_on_demand[it.first], true));
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fprintf(f, "%s [ shape=diamond, label=\"%s\" ];\n", it.first.c_str(), findLabel(wires_on_demand[it.first]));
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else
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fprintf(f, "%s [ shape=point ];\n", it.first.c_str());
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}
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@ -537,11 +555,16 @@ struct ShowPass : public Pass {
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log(" -prefix <prefix>\n");
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log(" generate <prefix>.* instead of ~/.yosys_show.*\n");
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log("\n");
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log(" -color <color> <wire>\n");
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log(" assign the specified color to the specified wire. The object can be\n");
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log(" -color <color> <object>\n");
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log(" assign the specified color to the specified object. The object can be\n");
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log(" a single selection wildcard expressions or a saved set of objects in\n");
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log(" the @<name> syntax (see \"help select\" for details).\n");
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log("\n");
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log(" -label <text> <object>\n");
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log(" assign the specified label text to the specified object. The object can\n");
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log(" be a single selection wildcard expressions or a saved set of objects in\n");
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log(" the @<name> syntax (see \"help select\" for details).\n");
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log("\n");
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log(" -colors <seed>\n");
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log(" Randomly assign colors to the wires. The integer argument is the seed\n");
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log(" for the random number generator. Change the seed value if the colored\n");
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@ -615,7 +638,7 @@ struct ShowPass : public Pass {
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color_selections.push_back(data);
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continue;
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}
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if (arg == "-label" && argidx+2 < args.size() && false) {
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if (arg == "-label" && argidx+2 < args.size()) {
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std::pair<std::string, RTLIL::Selection> data;
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data.first = args[++argidx], argidx++;
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handle_extra_select_args(this, args, argidx, argidx+1, design);
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