mirror of https://github.com/YosysHQ/yosys.git
Fixed comment/eol parsing in ilang frontend
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parent
d06258f74f
commit
af325bf206
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@ -109,7 +109,7 @@ void update_autoidx(const char *p);
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}
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<STRING>. { yymore(); }
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"#"[^\n]*\n /* ignore comments */
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"#"[^\n]* /* ignore comments */
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[ \t] /* ignore non-newline whitespaces */
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[\r\n]+ { return TOK_EOL; }
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@ -73,6 +73,9 @@ input:
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rtlil_frontend_ilang_yyerror("dangling attribute");
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};
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EOL:
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optional_eol TOK_EOL;
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optional_eol:
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optional_eol TOK_EOL | /* empty */;
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@ -82,7 +85,7 @@ design:
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/* empty */;
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module:
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TOK_MODULE TOK_ID TOK_EOL {
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TOK_MODULE TOK_ID EOL {
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if (current_design->modules.count($2) != 0)
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rtlil_frontend_ilang_yyerror("scope error");
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current_module = new RTLIL::Module;
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@ -94,7 +97,7 @@ module:
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} module_body TOK_END {
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if (attrbuf.size() != 0)
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rtlil_frontend_ilang_yyerror("dangling attribute");
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} TOK_EOL;
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} EOL;
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module_body:
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module_body module_stmt |
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@ -104,7 +107,7 @@ module_stmt:
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attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
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attr_stmt:
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TOK_ATTRIBUTE TOK_ID constant TOK_EOL {
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TOK_ATTRIBUTE TOK_ID constant EOL {
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attrbuf[$2] = *$3;
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delete $3;
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free($2);
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@ -115,7 +118,7 @@ wire_stmt:
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current_wire = new RTLIL::Wire;
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current_wire->attributes = attrbuf;
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attrbuf.clear();
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} wire_options TOK_ID TOK_EOL {
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} wire_options TOK_ID EOL {
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if (current_module->wires.count($4) != 0)
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rtlil_frontend_ilang_yyerror("scope error");
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current_wire->name = $4;
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@ -152,7 +155,7 @@ memory_stmt:
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current_memory = new RTLIL::Memory;
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current_memory->attributes = attrbuf;
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attrbuf.clear();
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} memory_options TOK_ID TOK_EOL {
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} memory_options TOK_ID EOL {
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if (current_module->memories.count($4) != 0)
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rtlil_frontend_ilang_yyerror("scope error");
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current_memory->name = $4;
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@ -170,7 +173,7 @@ memory_options:
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/* empty */;
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cell_stmt:
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TOK_CELL TOK_ID TOK_ID TOK_EOL {
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TOK_CELL TOK_ID TOK_ID EOL {
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if (current_module->cells.count($3) != 0)
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rtlil_frontend_ilang_yyerror("scope error");
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current_cell = new RTLIL::Cell;
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@ -181,21 +184,21 @@ cell_stmt:
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attrbuf.clear();
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free($2);
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free($3);
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} cell_body TOK_END TOK_EOL;
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} cell_body TOK_END EOL;
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cell_body:
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cell_body TOK_PARAMETER TOK_ID constant TOK_EOL {
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cell_body TOK_PARAMETER TOK_ID constant EOL {
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current_cell->parameters[$3] = *$4;
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free($3);
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delete $4;
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} |
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cell_body TOK_PARAMETER TOK_SIGNED TOK_ID constant TOK_EOL {
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cell_body TOK_PARAMETER TOK_SIGNED TOK_ID constant EOL {
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current_cell->parameters[$4] = *$5;
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current_cell->parameters[$4].flags |= RTLIL::CONST_FLAG_SIGNED;
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free($4);
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delete $5;
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} |
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cell_body TOK_CONNECT TOK_ID sigspec TOK_EOL {
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cell_body TOK_CONNECT TOK_ID sigspec EOL {
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if (current_cell->connections.count($3) != 0)
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rtlil_frontend_ilang_yyerror("scope error");
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current_cell->connections[$3] = *$4;
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@ -205,7 +208,7 @@ cell_body:
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/* empty */;
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proc_stmt:
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TOK_PROCESS TOK_ID TOK_EOL {
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TOK_PROCESS TOK_ID EOL {
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if (current_module->processes.count($2) != 0)
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rtlil_frontend_ilang_yyerror("scope error");
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current_process = new RTLIL::Process;
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@ -217,17 +220,17 @@ proc_stmt:
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case_stack.clear();
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case_stack.push_back(¤t_process->root_case);
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free($2);
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} case_body sync_list TOK_END TOK_EOL;
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} case_body sync_list TOK_END EOL;
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switch_stmt:
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attr_list TOK_SWITCH sigspec TOK_EOL {
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attr_list TOK_SWITCH sigspec EOL {
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RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
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rule->signal = *$3;
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rule->attributes = attrbuf;
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switch_stack.back()->push_back(rule);
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attrbuf.clear();
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delete $3;
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} switch_body TOK_END TOK_EOL;
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} switch_body TOK_END EOL;
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attr_list:
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/* empty */ |
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@ -239,7 +242,7 @@ switch_body:
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switch_stack.back()->back()->cases.push_back(rule);
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switch_stack.push_back(&rule->switches);
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case_stack.push_back(rule);
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} compare_list TOK_EOL case_body {
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} compare_list EOL case_body {
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switch_stack.pop_back();
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case_stack.pop_back();
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} |
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@ -262,27 +265,27 @@ case_body:
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/* empty */;
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assign_stmt:
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TOK_ASSIGN sigspec sigspec TOK_EOL {
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TOK_ASSIGN sigspec sigspec EOL {
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case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
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delete $2;
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delete $3;
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};
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sync_list:
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sync_list TOK_SYNC sync_type sigspec TOK_EOL {
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sync_list TOK_SYNC sync_type sigspec EOL {
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RTLIL::SyncRule *rule = new RTLIL::SyncRule;
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rule->type = RTLIL::SyncType($3);
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rule->signal = *$4;
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current_process->syncs.push_back(rule);
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delete $4;
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} update_list |
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sync_list TOK_SYNC TOK_ALWAYS TOK_EOL {
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sync_list TOK_SYNC TOK_ALWAYS EOL {
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RTLIL::SyncRule *rule = new RTLIL::SyncRule;
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rule->type = RTLIL::SyncType::STa;
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rule->signal = RTLIL::SigSpec();
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current_process->syncs.push_back(rule);
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} update_list |
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sync_list TOK_SYNC TOK_INIT TOK_EOL {
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sync_list TOK_SYNC TOK_INIT EOL {
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RTLIL::SyncRule *rule = new RTLIL::SyncRule;
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rule->type = RTLIL::SyncType::STi;
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rule->signal = RTLIL::SigSpec();
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@ -298,7 +301,7 @@ sync_type:
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TOK_EDGE { $$ = RTLIL::STe; };
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update_list:
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update_list TOK_UPDATE sigspec sigspec TOK_EOL {
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update_list TOK_UPDATE sigspec sigspec EOL {
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current_process->syncs.back()->actions.push_back(RTLIL::SigSig(*$3, *$4));
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delete $3;
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delete $4;
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@ -416,7 +419,7 @@ sigspec_list:
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};
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conn_stmt:
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TOK_CONNECT sigspec sigspec TOK_EOL {
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TOK_CONNECT sigspec sigspec EOL {
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if (attrbuf.size() != 0)
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rtlil_frontend_ilang_yyerror("dangling attribute");
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current_module->connections.push_back(RTLIL::SigSig(*$2, *$3));
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